서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
    Engineer, ABOV Semiconductor Co.
    2020.08, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
                   - Thesis Title : "Embedded SoC Architecture Based on Hardware Accelerator"
    2018.09 - 2020.08, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2018.03 - 2020.08, Research Assistant, SoC Platform Lab, Seoul National University of Science and Technology.
    2016.02, B.S. in Electronic Engineering, Korea Polytech University.

  [Research Interests]
    SoC Design
    Graphics Accelerator
    Signal Processing Accelerator
    Compression Accelerator

  [Projects]
   - 뉴로모픽 기반 임베디드 인공지능 모듈 및 시스템 기술 개발, 산업통상자원부, 2019-2021.
   - 고성능컴퓨팅(HPC)을 위한 멀티코어 하드웨어 가속기 핵심 기술 개발, 과학기술정보통신부, 2019-2022.
   - 저전력 독립운용이 가능한 내장형 인공지능 모듈 및 내비게이션 응용 서비스 기술 개발, 산업통상자원부, 2017-2020.
   - 호흡치료기 디바이스용 경량 SW-SoC 솔루션 개발, 산업통상자원부, 2017-2020.

  [Publications]
International Journal Papers
  3.  "The Design of a 2D Graphics Accelerator for Embedded Systems",
     Hyun Woo Oh, Ji Kwang Kim, Gwan Beom Hwang, and Seung Eun Lee,
      Electronics, Vol.10, No. 4, Feb. 2021.
  2.  "Lossless Decompression Accelerator for Embedded Processor with GUI",
     Gwan Beom Hwang, Kwon Neung Cho, Chang Yeop Han, Hyun Woo Oh, Young Hyun Yoon, and Seung Eun Lee,
      Micromachines, Vol. 12, No. 2, Jan. 2021.
  1.  "Design of Low-Power SoC for Wearable Healthcare Device",
     Ji Kwang Kim, Jung Hwan Oh, Gwan Beom Hwang, Oh Seong Gwon, and Seung Eun Lee,
      Journal of Circuits, Systems, and Computers (JCSC), Vol. 29, No. 6, May. 2020.

Chip Design Contest
  1. "Design of a Programmable Finger Gesture Recognition System for Embedded Devices",
      Ji Kwang Kim, Jung Hwan Oh, Young Hyun Yoon, Gwan Beom Hwang, Su Yeon Jang, and Seung Eun Lee
      15th International SoC Design Conference (ISOCC 2018), Daegu NOV, 2018.

Tech note
  5.  Gwan Beom HWANG, "Inflate-Decompression_Guideline", Seoultech, Feb. 2020.
  4.  Gwan Beom HWANG, "Inflate-Decompression_UserManual", Seoultech, Feb. 2020.
  3.  Gwan Beom HWANG, "Integrated Circuits Trainning Material", Fall. 2019.
  2.  Gwan Beom HWANG, "Design Compiler tutorial", Seoultech, May. 2019.
  1.  Gwan Beom HWANG, "VCS Verilog Encryption", Seoultech, Oct. 2018.

  [Presentations]
  3. "Cortex-M0 Designstart 기반의 SoC 플랫폼 설계",Seoultech, Spring, 2019
  2. "2D Line Draw Hardware Accelerator for Tiny Embedded Systems",
     International Conference on Consumer Electronics (ICCE2019), Las Vegas, NV, USA, Jan. 2019.
  1. "Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling",CSL meeting, Dec, 2018

  [Skills]
   High-level programming language : C/C++
   Hardware description language : Verilog
   Analysis language : MATLAB
   FPGA design tools : Synplify, Quartus II, Vivado
   EDA tools : ModelSim, NCsim, VCS, Design Compiler, Astro, IC Compiler I/II
   PCB design tools : ORCAD Pspice Designer, Allegro PCB Designer, PADS

  [Training]
   2019.05.28-05.30 - [Synopsys] IC Compiler II를 활용한 Block-level Auto P&R, IDEC.
   2019.03.04-03.08 - [IDEC 연구원 교육] Cell-Based Chip Design Flow, IDEC.
   2019.02.11-02.12 - Cortex-M0 DesignStart 기반의 SoC플랫폼 구성 및 활용, IDEC.
   2019.01.21-01.31 - 인피니언 연계 자동차용 반도체 전문인력 양성과정(심화과정), KSIA.
   2018.11.26-11.30 - [IDEC 연구원 교육] Cell-Based Chip Design Flow, IDEC.
   2018.08.10-08.14 - Full-custom 설계 실습, IDEC.
   2018.07.02-07.04 - 스마트 모바일 AP 구조 및 주변장치 응용, IDEC.

  [Courses]
    Computer Programming(C Programming), Digital Engineering and Hands-on, Engineering Mathmatics,
    Electromagnetics, Electronic Circuits and Practice, Communication theory, Semiconductor Engineering,
    Signals and Systems, VHDL and Hands-on, Microprocessor, Digital Communication, Circuits theory,
    DSP System and Hands-on, Image Signal Processing Application, SoC Design and Hands-on

  [Chips]

5. "Implementation of Lossless Decompression Accelerator Based on Inflate Algorithm"

   - Designer : Hwang Gwan Beom, Choi Do Young, Oh Hyun Woo, Han Chang Yeop
   - Technology : Samsung 65nm CMOSRF (1-poly 8-metal)
   - Tape Out : 2020. 9. 14
   - Power Supply : 1.8V
   - Core Size : 4mm x 4mm

4. "High-Speed automobile communication based on CAN-FD Controller"

   - Designer : Choi Do Young, Yoon Young Hyun, Hwang Gwan Beom, Cho Kwon Neung
   - Technology : TSMC 180nm BCDMOS
   - Tape Out : 2020. 5. 13
   - Power Supply : 2.5V
   - Core Size : 2.5mm x 5mm

3. "A Low Power AI Processor for Embedded System"

   - Designer : Yoon Young Hyun, Hwang Gwan Beom, Choi Do Young
   - Technology : Samsung 65nm CMOSRF (1-poly 8-metal)
   - Tape Out : 2019. 9. 16
   - Power Supply : 1.8V
   - Core Size : 4mm x 4mm

2. "A Low Power SoC for Digital Signal Processing in Embedded System"

   - Designer : Hwang Gwan Beom, Yoon Young Hyun, Han Chang Yeop
   - Technology : Magnachip hynix 0.18um CMOS
   - Tape Out : 2019. 6. 17
   - Power Supply : 3.3V
   - Core Size : 3.8mm x 3.8mm

1. "A Low Power AI Processor for face expression recognition based on k-NN and RBF"

   - Designer : Yoon Young Hyun, Jang Su Yeon, Han Chang Yeop, Hwang Gwan Beom
   - Technology : Magnachip hynix 0.35um CMOS
   - Tape Out : 2019. 1. 14
   - Power Supply : 3.3V
   - Core Size : 5mm x 4mm

Computer Architecture Laboratory