서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
    Research Engineer, Hyundai MOBIS.
    2016.02, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
                    - Thesis Title : "A Study on Hardware Acceleration of Lempel-Ziv Compression Algorithm"
    2014.02 - 2014.11, Researcher, Software Device Research Center, Korea Electronics Technology Institute.
    2014.02, Bachelor of Science in Electronic Engineering, Seoul National University of Science and Technology.
    2012.03 - 2016.02, Research Assistant, SoC Platforms Lab., Seoul National University of Science and Technology.

  [Research Interests]
   - Hardware Accelerators
   - Network-on-Chips

  [Projects]
    - 폭증스트림 데이터의 실시간 고가용 처리 서비스를 제공하는 다수 서버 분산 메모리의 통합 캐쉬 가상화 기술 기반 특화 응용 SW 개발, 미래창조과학부, 2012-2015.
    - 단일 노드 48TB 이상을 지원하는 개방형 하둡 스토리지 어플라이언스 개발, 미래창조과학부, 2013-2015.
    - 주력산업 고도화를 위한 SoC 결합형 임베디드SW 핵심기술 개발 및 산업생태계 개선, 산업통상자원부, 2014-2015.
    - 스마트키 기능을 포함하는 밴드형 웨어러블 디바이스 및 핵심기술 개발, 산업통상자원부, 2014-2015.

  [Awards]
    2012. Wearable Computer Contest - Silver Award (Hosted by Ministry of Knowledge Economy)
    2014. Altera Design Contest - Excellence Award (Hosted by Altera Korea and Axios)

  [Publications]
  International Journal Papers
  6.  "Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression",
     Sang Muk Lee, Ji Hoon Jang, Jung Hwan Oh, Ji Kwang Kim and Seung Eun Lee,
      IEICE Electronics Express(ELEX), Vol.14, No.11, pp.20170399, May. 2017.
  5.  "Design of a DMA Controller for Loss-less Image Processing",
     Seong Mo Lee, Ji Hoon Jang, Sang Muk Lee, Jung Hwan Oh, and Seung Eun Lee,
      Journal of Integrated Circuits and Systems (JICAS), Vol.02, No.2, pp.1-6, 2016.
  4.  "Compression Accelerator for Hadoop Appliance",
     Sang Don Kim, Seong Mo Lee, Sang Muk Lee, Ji Hoon Jang, Jae Gi Son, Yonug Hwan Kim and Seung Eun Lee,
     Lecture Notes in Computer Science, vol.8662, pp 416-423. 2014.
  3.  "In-time Transaction Accelerator Architecture for RDBMS",
     Su Jin Kim, Seong Mo Lee, Ji Hoon Jang, Yeong Seob Jeong, Sang Don Kim, and Seung Eun Lee,
     Lecture Notes in Electrical Engineering, vol. 260, pp. 329-334, 2013.
  2.  "mrGlove: FPGA-based data glove for heterogeneous devices",
     Seong Mo Lee, Ji Hoon Jang, Dae Young Park, Sang Don Kim, Ju Seong Lee, Seon Kyeong Kim, and Seung Eun Lee,
     Lecture Notes in Electrical Engineering, vol. 260, pp. 341-345, 2013.
  1.  "Intra-body Communication for Personal Area Network",
     Sang Don Kim, Ju Seong Lee, Yeong Seob Jeong, Ji Hoon Jang, and Seung Eun Lee,
     Lecture Notes in Electrical Engineering, vol. 260, pp. 335-339, 2013.

  International Conference Papers
  5.  "A LZ4 Compression Acceleration Engine",
     Jung Hwan Oh, Ji Hoon Jang, Jung Woo Shin, and Seung Eun Lee,
     13th International SoC Design Conference (ISOCC 2016), Jeju, Korea, Oct. 2016.
  4.  "Live Demonstration : An FPGA based Hardware Compression Accelerator for Hadoop System",
     Sang Muk Lee, Jung Hwan Oh, Ji Hoon Jang, Seong Mo Lee, and Seung Eun Lee,
     13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju, Korea, Oct. 2016.
  3.  "An FPGA based Compression Accelerator for Forex Trading System",
     Ji Hoon Jang, Seong Mo Lee, Oh Seong Gwon, and Seung Eun Lee,
     13th International Conference on Information Technology (ITNG 2016), Las Vegas, USA, Apr. 2016.
  2.  "Design of an EMG Recognition System for Human-Smartphone Interface",
     Seong Mo Lee, Sang Don Kim, Ji Hoon Jang, Sang Muk Lee, and Seung Eun Lee,
     12th International SoC Design Conference (ISOCC 2015), Gyeongju, Korea, Nov. 2015.
  1.  "Accelerating Forex Trading System Through Transaction Log Compression",
     Ji Hoon Jang, Sang Muk Lee, Sang Don Kim, Oh Seong Gwon, Eunnuri Ko, Seong Mo Lee, Jung Woo Shin, and Seung Eun Lee,
     11th International SoC Design Conference (ISOCC 2014), Jeju, Korea, Nov. 2014.

  Korean Conference Papers
  3.  하둡 클러스터를 위한 마이크로서버 구조 연구,
     장지훈, 김영환, 전기만, 손재기, 이승은,
     2015년 하계종합학술대회, 2015년 6월.
  2.  LZ4 Compression Accelerator for Hadoop Systems,
     Ji Hoon Jang, Seong Mo Lee, Sang Don Kim, and Seung Eun Lee,
     제1회 Korea ACM SIGARCH Chapter 워크샵, 2015년 1월.
  1.  FX 마진거래 시스템을 위한 하드웨어 가속기 구조,
     장지훈, 이상묵, 권오성, 김상돈, 이성모, 정혜동, 이승은,
     2014년 SoC 학술대회, 2014년 5월.

  Patents
  3.   문자열 압축 및 해제를 위한 방법 및 장치
           (METHOD AND APPARATUS FOR ENCODING AND DECODING STRINGS)
           Registration No. 10-1705461, Feb. 2017, Korea (right owned by SeoulTech)
  2.   APPARATUS AND METHOD FOR ACCELERATING HARDWARE COMPRESSION BASED ON HADOOP
           Application No. 6-1-2015-0043962-65, Aug. 2015, PCT (right owned by SeoulTech and DFOCUS)
  1.   하둡 기반 하드웨어 압축 고속화 장치 및 방법
           (APPARATUS AND METHOD FOR ACCELERATING HARDWARE COMPRESSION BASED ON HADOOP)
           Registration No. 10-1727508, Apr. 2017, Korea (right owned by SeoulTech)

  Copyrighted Softwares
  1.  고속 엘지4(LZ4) 압축 회로(프로그램)
           Registration No. C-2015-018807, Jul. 2015, Korea (right owned by SeoulTech)

  [Presentations]
  7.   "Dynamic Traffic Distribution among Hierarchy Levels in Hierarchical Networks-on-Chip", SPL meeting. Oct. 2014.
  6.   "ASIC Back-end design(Astro)", SPL meeting. Mar. 2014.
  5.   "Analysis and evaluation of circuit switched NoC and packet switched NoC", SPL meeting. Jan. 2014.
  4.   "Client Rendering Method for Desktop Virtualization Services", SPL meeting. Apr. 2013.
  3.   "Flattened Butterfly Topology for On-Chip Networks", SPL meeting. Mar. 2013.
  2.   "NoC-Out: Microarchitecting a Scale-Out Processor", SPL meeting. Jan. 2013.
  1.   "Cloud Computing", SPL meeting. Jul. 2012.

  [Skills]
    - FPGA Prototyping
    - ASIC Design
    - EDA tools: OrCAD PSpice, Design Compiler, VCS, Astro
    - Analysis Language: MATLAB, LabVIEW
    - High-level Computer Language: C, JAVA

  [Training]
    2013.01.23 - 01.24 IAR Embedded Workbench Basic training, IAR Systems.
    2013.01.29 - 01.31 PrimeTime Basic training, ETRI IT-SoC Academy.
    2013.05.08 - 05.10 ZYNQ Basic training, RAPA ATIC.
    2014.02.11 - 02.13 IC Compiler Basic training, IDEC.
    2014.07.21 - 07.25 MPW Design training, IDEC.
    2014.11.15 CMOS 아날로그 집적회로 실무를 위한 이론 및 실습 I, IDEC.
    2014.11.22 CMOS 아날로그 집적회로 실무를 위한 이론 및 실습 II, IDEC.
    2015.01.12 - 01.14 Full-Custom 설계 Flow 교육, IDEC.
    2016.01.04 - 02.04 인피니언 연계 자동차용 반도체 전문인력 양성 과정, Infineon Korea.

  [Courses]
    Circuit Analysis, Electro Magnetics, Logic Design, Computer Application System Design, Microwave Engineering, Microprocessor,
    Signal Processing, Digital Signal Processing, Electronic Circuit, Control Engineering, Computer Architecture, Power Electronics,
    Biomedical Instrumentation, Operationg systems, Internet Protocol, Communication System, Image Processing, Embedded Systems,
    Capstone Design, Thin-film Transistor Engineering, Probability and Random Process, Advanced Computer Architecture, Real-time Operating Systems,
    Topics in Artificial Intelligence, Network-on-Chip Design, Digital Signal Processor Application, and Fault Tolerant Processor Design

  [Chips]

4. "LZ4 Compression Engine"

   - Designer : Jang Ji Hoon, Lee Seong Mo, Lee Sang Muk, Shin Jung Woo
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2015. 9. 7
   - Power Supply : 1.8V, 3.3V
   - Core Size : 3.8mm x 3.8mm
   - Operating Frequency : 50MHz

3. "DMA Controller for Image Data Processing"

   - Designer : Lee Seong Mo, Jang Ji Hoon
   - Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
   - Tape Out : 2015. 6. 8
   - Power Supply : 3.3V
   - Core Size : 3mm x 2mm
   - Operating Frequency : 50MHz

2. "LZ4 Compression Accelerator for Hadoop Storage Appliance"

   - Designer : Jang Ji Hoon
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2014. 11. 24
   - Power Supply : 1.8V
   - Core Size : 0.6mm x 1.5mm
   - Operating Frequency : 50MHz

1. "Cloud Device SoC for Zero-Client"

   - Designer : Kim Sang Don, Jang Ji Hoon
   - Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
   - Tape Out : 2014. 6. 30
   - Power Supply : 3.3V
   - Core Size : 1.8mm x 1.6mm
   - Operating Frequency : 50MHz

Computer Architecture Laboratory