서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
    2019.01 - present, Engineer, Samsung Electronics Co, Memory Division
    2019.02, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
                   - Thesis Title : "Low-power SoC Architecture Based on Hardware Accelerator"
    2017.03 - 2019.02, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2016.02 - 2019.02, Research Assistant, SoC Platfrom Lab, Seoul National University of Science and Technology.

  [Research Interests]
   Digital System Design
   Failure Analysis
   Digial Singal Processing

  [Projects]
   - 저전력 독립운용이 가능한 내장형 인공지능 모듈 및 내비게이션 응용 서비스 기술 개발, 산업통상자원부, 2017-2020.
   - Classified Topic, 현대엔지비, 2017-2018.
   - 호흡치료기 디바이스용 경량 SW-SoC 솔루션 개발, 산업통상자원부, 2017-2020.
   - 스마트키 기능을 포함하는 밴드형 웨어러블 디바이스 및 핵심기술 개발, 산업통상자원부, 2014-2017.
   - 국산 CPU코어 내장 수 mW급 저전력 모바일 헬스케어 SOC개발, 산업통상자원부, 2015-2017.
   - SoC의 신뢰성 확보를 위한 오류율 분석 플랫폼 개발, 미래창조과학부, 2014-2017.

  [Publications]
International Journal Papers
  4.  "The Design of a 2D Graphics Accelerator for Embedded Systems",
     Hyun Woo Oh, Ji Kwang Kim, Gwan Beom Hwang, and Seung Eun Lee
      Electronics, Vol.10, No.4, Feb. 2021.
  3.  "Energy Efficient and Low-Cost Server Architecture for Hadoop Storage Appliance",
     Do Young Choi, Jung Hwan Oh, Ji Kwang Kim, and Seung Eun LEE,
      KSII Transactions on Internet and Information Systems (TIIS), Vol. 14, No. 12, Dec. 2020.
  2.  "Design of Low-Power SoC for Wearable Healthcare Device",
     Ji Kwang Kim, Jung Hwan Oh, Gwan Beom Hwang, Oh Seong Gwon, and Seung Eun Lee,
      Journal of Circuits, Systems and Computers(JCSC), Vol. 29, No. 6, May. 2020.
  1.  "Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression",
     Sang Muk Lee, Ji Hoon Jang, Jung Hwan Oh, Ji Kwang Kim, and Seung Eun Lee,
      IEICE Electronics Express(ELEX), Vol.14, No.11, pp.20170399, May. 2017.

  International Conference Papers
  7. "An FPGA-based Electronic Control Unit Controller for Automotive Systems",
      Jung Hwan Oh, Young Hyun Yoon, Ji kwang Kim, Hyung Bin Ihm, Shin Hye Jeon, Tae Heon Kim, and Seung Eun Lee
     37th IEEE International Conference on Consumer Electronics (ICCE 2019), Las Vegas, Nevada, USA, Jan, 2019.
  6. "2D Line Draw Hardware Accelerator for Tiny Embedded Systems",
      Ji kwang Kim, Jung Hwan Oh, Jun Hyeok Yang, and Seung Eun Lee
     37th IEEE International Conference on Consumer Electronics (ICCE 2019), Las Vegas, Nevada, USA, Jan, 2019.
  5. "In-System Remote Reconfiguration for Automotive Device",
      Young Hyun Yoon, Jung Hwan Oh, Ji kwang Kim, Hyung Bin Lhm, Shin Hye Jeon, Tae Heon Kim, and Seung Eun Lee
     37th IEEE International Conference on Consumer Electronics (ICCE 2019), Las Vegas, Nevada, USA, Jan, 2019.
  4. "Real-time PPG Monitoring System for Mobile Healthcare Devices",
      Ji kwang Kim, Jung Hwan Oh, Ohseong Gwon, Jung Wung Yang, and Seung Eun Lee
     21st International Symposium on Consumer Electronics (ISCE 2017), Kuala Lumpur, Malaysia, Nov. 2017.
  3. "Live Demonstration : An FPGA Based Hardware Compression Accelerator for Hadoop System",
     SangMuk Lee, Jung Hwan Oh, Ji Hoon Jang, Seong Mo Lee, Ji Kwang Kim, and Seung Eun Lee
     13th IEEE Asia Pacific Conference on Circuits and Systems (APPCAS 2016), Jeju, Oct. 2016.
  2. "Live Demonstration : AHB based Digital Filter for Low Power Mobile Healthcare System",
     Oh Seong Gwon, Ji Kwang Kim, Jung Woo Shin, and Seung Eun Lee
     13th IEEE Asia Pacific Conference on Circuits and Systems (APPCAS 2016), Jeju, Oct. 2016.
  1. "Design of an Area-Efficient Hardware Filter for Embedded System",
     Ji Kwang Kim, Oh Seong Gwon, and Seung Eun Lee
     13th International SoC Design Conference (ISOCC 2016), Jeju, Oct. 2016.

  Korean Conference Papers
  3. "모바일 기기를 위한 JPEG하드웨어 인코딩 가속기 설계",
     이재원, 김지광, 오정환, 신정우, 이승은
     2017년 대한전자공학회 하계종합학술대회, 2017 7월.
  2. "다중 채널 신호처리를 위한 하드웨어 가속기 구조",
     김지광, 이승은
     2017년 SoC 학술대회, 2017 5월.
  1. "고정소수점 IIR 대역통과 필터설계와 소수부 비트 수에 따른 주파수응답 분석",
     김지광, 권오성, 신정우, 이승은
     2016년 SoC 학술대회, 2016 5월.

  Chip Design Contest
  2. "Design of a Programmabel Finger Gesture Recognition System for Embedded Devices",
     Ji Kwang Kim, Jung Hwan Oh, Young Hyun Yoon, Gwan Beom Hwang, Su Yeon Jang, and Seung Eun Lee
     15th International SoC Design Conference (ISOCC 2018), Daegu, Nov, 2018.
  1. "Design of Read-out IC for Wearable Computing",
     Ji Kwang Kim, Jung Hwan Oh, Seung Eun Lee
     14th International SoC Design Conference (ISOCC 2017), Seoul, Nov, 2017.

  Patents
  2.   Apparatus and Method for Recognition of Gesture
      Applicatoin No. 10-2018-0079553, Jul. 2018, Korea (right owned by SeoulTech)
  1.   Apparatus for Inspecting Error of System on Chip
      Registration No. 10-1943715, Jan. 2019, Korea (right owned by SeoulTech)

  Registered Copyright
  SW.1   헬스케어 시스템을 위한 디지털 필터 회로
      Registration No. C-2016-025453, Oct, 2016, Korea(right owned by SeoulTech)

Tech. Notes
  1.  Ji Kwang KIM, "HPU : Digital Filter Guideline," Jan, 2017.

  [Presentations]
  2. "MICRO 2017 Review: Microarchitecture Level Reliability Assessment",,SPL meeting, oct, 2017
  1. "Analytical Fault Modeling for Resilient System-on-Chip Design",,SPL meeting, Sep, 2016

  [Skills]

    High-level programming Language : C, JAVA

    Hardware Description Language : Verilog

    Analysis Language : MATLAB, Python

    FPGA design tools : Synplify, QuartusII, Xilinx Vivado

    EDA tools : ModelSim, NCsim, VCS, Design Compiler, Astro, IC Compiler

    PCB design tools : ORCAD Pspice Designer, Allegro PCB Designer

[Training]


    2017.12.18-12.20  AI 하드웨어가속기 칩 구조 설계실습, ETRI.

    2017.08.21-09.01  인피니언 연계 자동차용 반도체 전문인력 양성과정(심화과정), KSIA.

    2017.08.09-08.11  Xlinx ZYNQ Device 설계 교육계, IDEC.

    2017.07.03-07.14  인피니언 연계 자동차용 반도체 전문인력 양성과정(기본과정), KSIA.

    2017.03.23-03.23  반도체 기반 IoT 플랫폼(삼성 IoT 플랫폼 ARTIK 활용), IDEC.

    2017.03.07-03.08  OrCAD (Allegro) PCB를 이용한 PCB 설계, IDEC.

    2017.02.14-02.15  [IDEC 연구원 교육]MS180 Digital Layout 설계 방법, IDEC.

    2017.02.07-02.09  기가비트 이더넷 제어기 설계와 응용설계, IDEC.

    2017.01.02-01.06  MPW Design Training, IDEC.

    2016.08.16-08.19  Cortex_M0 DesignStart 기반의 SoC플랫폼 구성 및 활용, IDEC.

    2016.08.01-08.03  IC Compiler 사용법 및 활용예, IDEC. 

    2016.07.11-07.14  스마트 모바일 AP기반 SoC구조 및 주변장치 응용, IDEC. 

    2016.07.04-07.07  지능형 웨어러블 시스템 설계, IDEC.
 
    2016.06.27-06.30  Verilog HDL 이론 및 응용, IDEC.

    2016.03.28-03.31  MPW Design Training, IDEC. 

    2016.02.25-02.25  Training for EISC development environment, ADChips.

  [graduate Courses]
   VLSI for Digital Signal Processing, Semiconductor Integrated Circuit Design II, Speech and Audio Processing
   Advanced Computer Architecture, Embedded Software, Computer Applied Circuit Design
   Special topic in Network-on-Chip, Advanced Digital Signal Processing

  [Undergraduate Courses]
    Engineering Mathmatics, Electrical and Electronic Experiments, Electromagnetics,
    Engineering Circuit Analysis, Electronic Circuits,
    Semiconductor Engineering,
    Microwave Engineering, RF Circuit Design

    Digital Logic Circuit, Microprocessor, Application of Microprocessor,
    Computer Application System Design, Computer Architecture,
    Operating System, Embedded System,
    Computer Programming(C Programming), Mobile Programming(JAVA Programming),
    Signals and Systems, Digital Signal Processing, Image Processing,
    Communication system, Digital Mobile Communication,

    Capstone Design
  [Chips]

4. "Programmable Finger Gesture Recognition based on k-nearest neighbors algorithm"

   - Designer : Kim Ji Kwang, Oh Jung Hwan
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2017. 9. 18
   - Power Supply : 3.3V
   - Core Size : 3.8mm x 3.8mm

3. "Low-power hardware accelerator for Biomedical Signal Processing"

   - Designer : Kim Ji Kwang, Gwon Oh Sung, Oh Jung Hwan
   - Technology : SMIC 0.11um CMOS (1-poly 6-metal)
   - Tape Out : 2017. 9. 11
   - Digital Power Supply : 1.2V
   - Analog Supply Voltage : 3.3V
   - Core Size : 3.5mm x 3.5mm

2. "Multi-purpose Controllers for Subminiature Sensor Embedded in Wearable Device"

   - Designer : Kim Ji Kwang, Oh Jung Hwan
   - Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
   - Tape Out : 2016. 6. 13
   - Power Supply : 3.3V
   - Core Size : 5mm x 4mm

1. "HPU01: Low-power Processor for Healthcare Wearable Device"

   - Designer : Gwon Oh Sung, Kim Ji Kwang
   - Technology : SMIC 0.11um CMOS (1-poly 8-metal)
   - Tape Out : 2016. 6. 9
   - Power Supply : 1.2V
   - Core Size : 3.5mm x 3.5mm

Computer Architecture Laboratory