Seoul National University of Science and Technology
232 Gongneung-ro, Nowon-gu, 01811, Seoul, KOREA
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High-level programming Language : C, JAVA
Hardware Description Language : Verilog
Analysis Language : MATLAB, Python
FPGA design tools : Synplify, QuartusII, Xilinx Vivado
EDA tools : ModelSim, NCsim, VCS, Design Compiler, Astro, IC Compiler
PCB design tools : ORCAD Pspice Designer, Allegro PCB Designer
2017.12.18-12.20 AI 하드웨어가속기 칩 구조 설계실습, ETRI.
2017.08.21-09.01 인피니언 연계 자동차용 반도체 전문인력 양성과정(심화과정), KSIA.
2017.08.09-08.11 Xlinx ZYNQ Device 설계 교육계, IDEC.
2017.07.03-07.14 인피니언 연계 자동차용 반도체 전문인력 양성과정(기본과정), KSIA.
2017.03.23-03.23 반도체 기반 IoT 플랫폼(삼성 IoT 플랫폼 ARTIK 활용), IDEC.
2017.03.07-03.08 OrCAD (Allegro) PCB를 이용한 PCB 설계, IDEC.
2017.02.14-02.15 [IDEC 연구원 교육]MS180 Digital Layout 설계 방법, IDEC.
2017.02.07-02.09 기가비트 이더넷 제어기 설계와 응용설계, IDEC.
2017.01.02-01.06 MPW Design Training, IDEC.
2016.08.16-08.19 Cortex_M0 DesignStart 기반의 SoC플랫폼 구성 및 활용, IDEC.
2016.08.01-08.03 IC Compiler 사용법 및 활용예, IDEC.
2016.07.11-07.14 스마트 모바일 AP기반 SoC구조 및 주변장치 응용, IDEC.
2016.07.04-07.07 지능형 웨어러블 시스템 설계, IDEC.
2016.06.27-06.30 Verilog HDL 이론 및 응용, IDEC.
2016.03.28-03.31 MPW Design Training, IDEC.
2016.02.25-02.25 Training for EISC development environment, ADChips.
4. "Programmable Finger Gesture Recognition based on k-nearest neighbors algorithm"
- Designer : Kim Ji Kwang, Oh Jung Hwan
- Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
- Tape Out : 2017. 9. 18
- Power Supply : 3.3V
- Core Size : 3.8mm x 3.8mm
3. "Low-power hardware accelerator for Biomedical Signal Processing"
- Designer : Kim Ji Kwang, Gwon Oh Sung, Oh Jung Hwan
- Technology : SMIC 0.11um CMOS (1-poly 6-metal)
- Tape Out : 2017. 9. 11
- Digital Power Supply : 1.2V
- Analog Supply Voltage : 3.3V
- Core Size : 3.5mm x 3.5mm
2. "Multi-purpose Controllers for Subminiature Sensor Embedded in Wearable Device"
- Designer : Kim Ji Kwang, Oh Jung Hwan
- Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
- Tape Out : 2016. 6. 13
- Power Supply : 3.3V
- Core Size : 5mm x 4mm