서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
   Engineer, Hanwha Corporation/Defense, Research&Engineering Center.
   2016.02, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
                   - Thesis Title : "Analytical Fault Modeling for Resilient System-on-Chip Design"
   2011.12 - 2016.02, Research Assistant, SoC Platforms Lab, Seoul National University of Science and Technology.
   2014.02, B.S. in Dept. of Electronic and Information Engineering, Seoul National University of Science and Technology.
   2013.08 - 2014.03, Research Intern, SoC Research Center, Korea Electronics Technology Institute (KETI).

  [Research Interests]
   Android OS
   Digital System Design
   Gigabit Ethernet MAC Core Architecture
   Fault Tolerance Processor

  [Projects]
  4.  Wearable infotainment platform based on EMG signal, Altera Korea and Axios, 2014.07 - 2014.11
   근전도 신호 측정을 위한 아날로그 회로 구현
   채널별 근전도 신호 분석을 위한 Classification 모듈 및 UART 모듈 구현
   블루투스 통신을 지원하는 어플리케이션 구현
  3.  SoC의 신뢰성 확보를 위한 오류율 분석 플랫폼 개발, 서울과학기술대학교, 2014-2017
   VPI기반 오류 탐색 function 개발
   논리게이트의 오류모델링 개발
  2.  단일 노드 48TB 이상을 지원하는 개방형 하둡 스토리지 어플라이언스 개발, 미래창조과학부, 2013-2015
   AXI4 Memory Mapped wrapper 모듈 설계
  1.  폭증스트림 데이터의 실시간 고가용 처리 서비스를 제공하는 다수 서버 분산 메모리의 통합 캐쉬 가상화 기술 기반 특화 응용 SW 개발, 미래창조과학부, 2012-2015
   ZC706 개발보드를 이용한 PCI Express 2.0 인터페이스 채널 구현

  [Awards]
   2014. Altera Design Contest - Excellence Award (Hosted by Altera Korea and Axios)
   2012. Wearable Computer Contest - Silver Award (Hosted by Ministry of Knowledge Economy(MKE))

  [Publications]
International Journal Papers
  5.  "Design of a DMA Controller for Loss-less Image Processing,"
     Seong Mo Lee, Ji Hoon Jang, Sang Muk Lee, Jung Hwan Oh, and Seung Eun Lee,
      Journal of Integrated Circuits and Systems (JICAS), Vol.02, No.2, pp.1-6, 2016.
  4.  "Survey of Fault-Injection Techniques for Resilient System-on-Chip Design,"
     Yeong Seob Jeong, Seong Mo Lee, and Seung Eun Lee,
     International Journal of Applied Engineering Research (IJAER), vol.10, no.17, pp.38377-38383, 2015.
  3.  "Compression Accelerator for Hadoop Appliance,"
     Sang Don Kim, Seong Mo Lee, Sang Muk Lee, Ji Hoon Jang, Jae Gi Son, Young Hwan Kim, and Seung Eun Lee,
     Lecture Notes in Computer Science, vol.8662, pp.416-423, 2014.
  2.  "mrGlove: FPGA-based data glove for heterogeneous devices,"
     Seong Mo Lee, Ji Hoon Jang, Dae Young Park, Sang Don Kim, Ju Seong Lee, Seon Kyeong Kim, and Seung Eun Lee,
     Lecture Notes in Electrical Engineering, vol.260, pp.341-345, 2013.
  1.  "In-time Transaction Accelerator Architecture for RDBMS,"
     Su Jin Kim, Seong Mo Lee, Ji Hoon Jang, Yeong Seob Jeong, Sang Don KIM, and Seung Eun Lee,
     Lecture Notes in Electrical Engineering, vol.260, pp.329-334, 2013.

International Conference Papers
  4. "Live Demonstration : An FPGA based Hardware Compression Accelerator for Hadoop System",
   Sang Muk Lee, Jung Hwan Oh, Ji Hoon Jang, Seong Mo Lee, and Seung Eun Lee
   13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju, Korea, Oct., 2016.
  3.  "Static Fault Analysis for Resilient System-on-Chip Design,"
     Seong Mo Lee, and Seung Eun Lee,
     12th International SoC Design Conference (ISOCC 2015), Gyeongju, Korea, Nov. 2015.
  2.  "Design of an EMG Recognition System for Human-Smartphone Interface,"
     Seong Mo Lee, Sang Don Kim, Ji Hoon Jang, Sang Muk Lee, and Seung Eun Lee,
     12th International SoC Design Conference (ISOCC 2015), Gyeongju, Korea, Nov. 2015.
  1.  "Accelerating Forex Trading System Through Transaction Log Compression,"
     Ji Hoon Jang, Sang Muk Lee, Sang Don Kim, Oh Seong Gwon, Eunnuri Ko, Seong Mo Lee, Jung Woo Shin, and Seung Eun Lee,
     11th International SoC Design Conference (ISOCC 2014), Jeju, Korea, Nov. 2014.

Korean Conference Papers
  6.  "내고장형 시스템반도체 설계를 위한 분석적인 고장 진단 방법,"
     이성모, 이승은,
     2015년 추계학술대회, 2015년 11월.
  5.  "오디오 비디오 브릿징을 위한 고속 JPEG 코덱 설계,"
     신정우, 이건하, 김상돈, 이성모, 장지훈, 이상묵, 이승은,
     2015년 SoC 학술대회, 2015년 5월.
  4.  "LZ4 Compression Accelerator for Hadoop Systems,"
     Ji Hoon Jang, Seong Mo Lee, Sang Don Kim, and Seung Eun Lee,
     제1회 Koera ACM SIGARCH Chapter 워크샵, 2015년 1월.
  3.  "Fault Analysis for Fault-tolerant System-on-Chip Design,"
     Seong Mo Lee, and Seung Eun Lee,
     제1회 Koera ACM SIGARCH Chapter 워크샵, 2015년 1월.
  2.  "FX 마진거래 시스템을 위한 하드웨어 가속기 구조,"
     장지훈, 이상묵, 권오성, 김상돈, 이성모, 정혜동, 이승은,
     2014년 SoC 학술대회, 2014년 5월.
  1.  "영상인식시스템의 영상 데이터 처리를 위한 DMA 제어기 설계,"
     이성모, 이선영, 민경원, 이승은,
     2014년 SoC 학술대회, 2014년 5월.

Chip Design Contest
  1. "A DMA Controller for Loss-less Image Processing",
   Jung Hwan Oh, Seong Mo Lee, Ji Hoon Jang, Sang Muk Lee, and Seung Eun Lee
   International SoC Design Conference (ISOCC), Gyeongju, Korea, Nov., 2016.

Patents
  IP.3  SoC에서의 오류율 분석 방법
     (Method for analyzing error rate in System on Chip)
     Registration No. 10-1544649, Aug. 2015, Korea (right owned by SeoulTech)
  IP.2  Method of analyzing error rate in System on Chip
     US 9,671,447 B2, Jun. 2017, USA (right owned by SeoulTech)
  IP.1  SoC에서의 게이트 레벨 오류 모델링 방법
     (Method for modeling error of level of gate in System on Chip)
     Application No. 10-0162712, Dec. 2013, Korea (right owned by SeoulTech)

Registered Copyright
  SW.2  엑시4-스트림(AXI4-Stream) 메모리 인터페이스 변환회로
         Registration No. C-2015-018808, Aug. 2015, Korea (right owned by SeoulTech)
  SW.1  Motion recognition control using Bluetooth of smart phone
         Registration No. C-2013-000691, Jan. 2013, Korea (right owned by SeoulTech)

  [Presentations]
  12  "A Low-cost Mechanism Exploiting Narrow-width Values for Tolerating hard Faults in ALU",SPL meeting. May.2015.
  11  "Wearable infotainment platform based on EMG signal",Altera Design Contest. Dec.2014.

  10  "An NoC and Cache Hierarchy Substrate to Address Effective Virtualization and Fault-Tolerance",SPL meeting. Oct.2014.
  9  "영상인식시스템의 영상 데이터 처리를 위한 DMA 제어기 설계",2014 SoC 학술대회. 2014년 5월.
  8  "mrGlove:FPGA-based data glove for heterogeneous devices",International Conferfence on Embedded and Multimedia Computing (EMC-13). Aug. 2013.
  7  "Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices",SPL meeting. July.2013.
  6  "Soft Error Propagation and Correlation Estimation in Combinational Network",SPL meeting. July.2013.
  5  "Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - concept and theory of operation",SPL meeting. May.2013.
  4  "On-the-fly Composition of FPAG-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library",SPL meeting. Mar.2013.
  3  "Enhancing Cache Coherent Architectures with Access Patterns for Embedded Manycore Systems",SPL meeting. Jan.2013.
  2  "Design and Implementation of FPGA Based Interface Model for Scale-Free Network using I2C Bus Protocol on QuartusⅡ 6.0",SPL meeting. April.2012.
  1  "A New Approach to Realize UART",SPL meeting. Jan. 2012.

  [Skills]
   - EDA tools: ModelSim, ORCAD Pspice, QuartusII, Xilinx ISE
   - High-level Computer Language: C Programing
   - Analysis Language: MATLAB
   - FPGA prototyping

  [Training]
   - ARM DS-5를 이용한 리눅스, 안드로이드 디버깅 기술, huins, June. 2015
   - Full-Custom 설계 Flow 교육, IDEC, Jan. 2015
   - CMOS 아날로그 집적회로 실무를 위한 이론 및 실습 Ⅱ, IDEC, Nov. 2014
   - IDEC MPW design, IDEC, Jul. 2014
   - Full-custom design(Basic), IDEC, Jul. 2013
   - Zynq Training(Basic), RAPA, May. 2013
   - PrimeTime Basic Education, ETRI, Jan. 2013
   - IAR Embedded Workbench seminar, IAR Systems Korea Co, Jan. 2013
   - Android App Development Education, IDEC, Aug. 2012

  [Graduate Courses]
   Thin-film transistor Engineering, Probability and Random Process, Advanced computer architecture, Real time operating system,
   Networks-on-Chip design, Topics in Artificial Intelligence, Digital Signal Processor Application, and Fault Tolerant Processor Design.

  [Undergraduate Courses]
   Computer Programming(C Programming), Digital Logic Circuit, Electromagnetics, Engineering Circuit Analysis, Engineering Programming(MATLAB),
   Electric Circuit Experiment, Semiconductor Engineering, Microprocessor, Computer Application System Design, Control System Engineering,
   Electronic Circuit, Signals and Systems, Computer Architecture, Digital Signal Processing(DSP), Operating System, Internet Protocol, Capstone Design,
   Biomedical Instrumentation, TCP/IP network programming, and Embedded System.

  [Chips]

2. "LZ4 Compression Engine"

   - Designer : Jang Ji Hoon, Lee Seong Mo, Lee Sang Muk, Shin Jung Woo
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2015. 9. 7
   - Power Supply : 1.8V, 3.3V
   - Core Size : 3.8mm x 3.8mm
   - Operating Frequency : 50MHz

1. "DMA Controller for Image Data Processing"

   - Designer : Lee Seong Mo, Jang Ji Hoon
   - Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
   - Tape Out : 2015. 6. 8
   - Power Supply : 3.3V
   - Core Size : 3mm x 2mm
   - Operating Frequency : 50MHz

Computer Architecture Laboratory