서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
    Junior Engineer, Core H/W Team, Hanwha Systems
    2023.02, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
                   - Thesis Title : "Research on Optimized Processor and Floating-point Unit Architecture for Embedded Systems"
    2021.03 - 2023.02, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2021.02, B.S. in Electronic and Information Engineering, Seoul National University of Science and Technology.
    2019.12 - 2023.02, Research Assistant, SoC Platform Lab, Seoul National University of Science and Technology.

  [Research Interests]
    Computer Programing
    Digital System Design
    Processor Architecture

  [Projects]
   - Development for Processing Software on AI Semiconductor Devices, Ministry of Science and ICT, 2022-2029.
   - Development of DRAM PIM Semiconductor Technology For Enhanced Computing Function for Edge, Ministry of Science and ICT, 2022-2025.
   - Developed Proximity/Healthcare Convergence Sensor SoC for TWS (True Wireless Stereo), Ministry of Trade, Industry and Energy, 2021-2023.
   - Next-Generation System Semiconductor Design Engineer Development Program, Ministry of Trade, Industry and Energy, 2021-2026.
   - Development of Embedded Artificial Intelligence Module and System Based on Neuromorphic, Ministry of Trade, Industry and Energy, 2019-2021.
   - Multi-core Hardware Accelerator for High-Performance Computing (HPC), Ministry of Science and ICT, 2019-2022.
   - Development of Light-weight SW-SoC Solution for Respiratory Medical Device, Ministry of Trade, Industry and Energy, 2017-2020.

  [Publications]
  International Journal Papers
  6.   "DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting",
   Hyun Woo Oh, Joungmin Park, and Seung Eun Lee,
    IEEE Transactions on Circuits and Systems II: Express Briefs, Early Access, pp. 1-5, 2024.
  5.   "The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension",
   Hyun Woo Oh, and Seung Eun Lee,
    IEEE Access, Vol.11, pp. 49409-49421, 2023.
  4.   "A Multi-Core Controller for an Embedded AI System Supporting Parallel Recognition",
   Suyeon Jang, Hyun Woo Oh, Young Hyun Yoon, Dong Hyun Hwang, Won Sik Jeong, and Seung Eun Lee,
    Micromachines, Vol.12, No.8, Jul. 2021.
  3.   "ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator",
   Dong Hyun Hwang, Chang Yeop Han, Hyun Woo Oh, and Seung Eun Lee,
    Micromachines, Vol.12, No.7, Jul. 2021.
  2.   "The Design of a 2D Graphics Accelerator for Embedded Systems",
   Hyun Woo Oh, Ji Kwang Kim, Gwan Beom Hwang, and Seung Eun Lee,
    Electronics, Vol.10, No.4, Feb. 2021.
  1.   "Lossless Decompression Accelerator for Embedded Processor with GUI",
   Gwan Beom Hwang, Kwon Neung Cho, Chang Yeop Han, Hyun Woo Oh, Young Hyun Yoon, and Seung Eun Lee,
    Micromachines, Vol.12, No.2, Jan. 2021.

  International Conference Papers
  6.   "RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit",
   Hyun Woo Oh, Seongmo An, Won Sik Jeong, and Seung Eun Lee,
    ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2023), Vienna, Austria, Aug. 2023.
  5.   "Evaluation of Posit Arithmetic on Machine Learning based on Approximate Exponential Functions",
   Hyun Woo Oh, Won Sik Jeong, and Seung Eun Lee,
    19th International SoC Design Conference (ISOCC 2022), Gangneung, Korea, Oct. 2022.
  4.   "A Local Interconnect Network Controller for Resource-Constrained Automotive Devices",
   Kwon Neung Cho, Hyun Woo Oh, Jeongeun Kim, Young Woo Jeong, and Seung Eun Lee,
    40th International Conference on Consumer Electronics (ICCE 2022), Las Vegas, USA, Jan. 2022.
  3.   "Intelligent Transportation System based on an Edge AI",
   Young Woo Jeong, Hyun Woo Oh, Su Yeon Jang, and Seung Eun Lee,
    14th International Conference on Future Information & Communication Engineering (ICFICE 2022), Jeju, Korea, Jan. 2022.
  2.   "Vision-based Parking Occupation Detecting with Embedded AI Processor",
   Kwon Neung Cho, Hyun Woo Oh, and Seung Eun Lee,
    39th International Conference on Consumer Electronics (ICCE 2021), Online, Jan. 2021.
  1.   "Design of 32-bit Processor for Embedded Systems",
   Hyun Woo Oh, Kwon Neung Cho, and Seung Eun Lee,
    17th International SoC Design Conference (ISOCC 2020), Yeosu, Korea, Oct. 2020.

  Korean Conference Papers
  1.   "임베디드 인공지능 시스템을 이용한 지능형 교통 시스템을 위한 차량 번호판 인식",
   정영우, 고광현, 오현우, 조권능, 이승은,
   제 3회 반도체공학회 종합학술대회, Dec. 2020.

  [Awards]
    - 2020.10.13. President of the Institute of Semiconductor Engineers Award, 21st Korea Semiconductor Design Contest

  [Skills]
  Computer Languages
    - High-level Computer Language: C/C++, C#, JAVA, Python, Perl
    - Hardware Description Language: Verilog, Chisel
  EDA tools
    - Simulation: VCS, Verdi, ModelSim, Vivado, Verilator
    - FPGA: Quartus, Vivado, Vitis
    - ASIC Design: Design Compiler, Formality, PrimeTime, IC Compiler, IC Compiler II, Star RCXT, Virtuoso

  [Training]
    2023.12.09-12.09 - Design of High-speed Memory Interface, IDEC
    2021.11.01-11.05 - Cell-based Chip Design Flow for Samsung 28nm Process, IDEC
    2021.10.19-10.21 - [Synopsys] Block-level Auto P&R utilizing IC Compiler II, IDEC
    2021.07.05-07.09 - Cell-based Chip Design Flow, IDEC
    2021.06.30-07.02 - [Infineon] Automotive Semiconductor Expert Training - Basic Course, KSIA
    2020.08.10-08.14 - Cell-based Chip Design Flow, IDEC

  [Courses]
  Undergraduate
    Computer Programming(C Programming), Engineering Mathmatics, Electrical and Electronic Experiment,
    Electromagnetics, Logic Circuit, Signal System, Circuit Theory,
    Microprocessor, Computer Applications System Design, Digital Signal Processing, Semiconductor Engineering,
    Application of Microprocessors, Computer Architecture, Communication System, Mobile Communication Engineering,
    Machine Learning, Operating System, Mobile Programing, Embedded System, Image Processing, Integrated Circuit,
    Capstone Design(1), Capstone Design(2)
    Advanced Computer Architecture, Advanced Semiconductor Engineering, RF/Analog Integrated Circuits and Systems,
  Graduate
    SoC Design Methodology, High-speed Communication Circuit, Pattern Recognition,
    Resilient System Design, Probablility and Random Process, Advanced Artificial Intelligent Processors,
    Research for the Master's Degree I, Research for the Master's Degree(2)
  [Chips]

7. "A RISC-V Processor Supporting AMBA AXI Protocol for Embedded Systems"

   - Designer : Won Sik Jeong, Sun Beom Kwon, Hyun Woo Oh, Jeongeun Kim
   - Technology : Samsung 28nm RFCMOS (1-poly 8-metal)
   - Tape Out : 2022. 07. 18
   - Power Supply : 1.0V
   - Core Size : 2mm x 4mm

6. "Robot-Specific Processor for Autonomous Driving"

   - Designer : Youngwoo Jeong, Yue Ri Jeong, Hyun Woo Oh, Kwang Hyun Go
   - Technology : Samsung 28nm RFCMOS (1-poly 8-metal)
   - Tape Out : 2022. 07. 18
   - Power Supply : 1.0V
   - Core Size : 2mm x 4mm

5. "In-Vehicle Network Processor based on Cortex-M0"

   - Designer : Kwon Neung Cho, Jeong Eun Kim, Hyun Woo Oh
   - Technology : TSMC 180nm RFCMOS (1-poly 6-metal)
   - Tape Out : 2022. 03. 16
   - Power Supply : 1.8V
   - Core Size : 3.4mm x 3mm

4. "A Programmable Embedded AI Processor with Cortex-M0"

   - Designer : Kwon Neung Cho, Young Woo Jeong, Hyun Woo Oh, Chang Yeop Han
   - Technology : Samsung 28nm RFCMOS (1-poly 8-metal)
   - Tape Out : 2021. 07. 19
   - Power Supply : 1.0V
   - Core Size : 2mm x 4mm

3. "32-bit Processor with Posit Arithmetic Coprocessor for Embedded Systems"

   - Designer : Hyun Woo Oh, Jeong Eun Kim, Do Young Choi, Kwang Hyun Go
   - Technology : Samsung 28nm RFCMOS (1-poly 8-metal)
   - Tape Out : 2021. 07. 19
   - Power Supply : 1.0V
   - Core Size : 2mm x 4mm

2. "Implementation of Lossless Decompression Accelerator Based on Inflate Algorithm"

   - Designer : Gwan Beom Hwang, Do Young Choi, Hyun Woo Oh, Chang Yeop Han
   - Technology : Samsung 65nm RFCMOS (1-poly 8-metal)
   - Tape Out : 2020. 09. 14
   - Power Supply : 1.2V
   - Core Size : 4mm x 4mm

1. "Communication System with Simple and Fast Communication Error Check Code Based on CRC"

   - Designer : Chang Yeop Han, Kwon Neung Cho, Hyun Woo Oh
   - Technology : Magnachip Hynix 0.18um CMOS
   - Tape Out : 2020. 06. 01
   - Power Supply : 1.8V
   - Core Size : 3.4mm x 3.4mm

Computer Architecture Laboratory