서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
   Engineer, Samsung Advanced Institute of Technology (SAIT)
   2019.02, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
                   - Thesis Title : "Automotive SoC Architecture for In-Vehicle Networks"
   2017.03 - 2019.02, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
   2015.04 - present, Research Assistant, SoC Platform Lab, Seoul National University of Science and Technology.
   2013.03 - 2017.02, Undergraduate Student, Dept. of Electronic and Information Engineering, Seoul National University of Science and Technology.

  [Research Interests]
   System-on-Chip; Low-power and high-performance SoC, SoC for spiking neural networks, SoC for automotive system,
   hardware accelerator; low-power hardware accelerator, lz4 compression accelerator, machine learning accelerator,
   Multicore-based encryption accelerator, FPGA based implementation and optimization for high performance accelerators

  [Projects]
   - 저전력 독립운용이 가능한 내장형 인공지능 모듈 및 내비게이션 응용 서비스 기술 개발, 산업통상자원부, 2017-2020.
   - Classified Topic, 현대엔지비, 2017-2018.
   - 스마트키 기능을 포함하는 밴드형 웨어러블 디바이스 및 핵심기술 개발, 산업통상자원부, 2014-2017.
   - 국산 CPU코어 내장 수 mW급 저전력 모바일 헬스케어 SOC개발, 산업통상자원부, 2015-2017.
   - 단일노드 48TB 이상을 지원하는 개방형 하둡 스토리지 어플라이언스 개발, 미래창조과학부, 2013-2016.
   - 다중코어 암호연산기의 데이터 처리를 위한 스케줄링 기법 연구, 국가보안기술연구소, 2015-2015.

  [Publications]
International Journal Papers
  5.  "An FPGA-Based ECU for Remote Reconfiguration in Automotive Systems",
     Kwonneung Cho, Jeongeun Kim, Do Young Choi, Young Hyun Yoon, Jung Hwan Oh and Seung Eun Lee,
      Micromachines, Vol. 12, No. 1309, Oct. 2021.
  4.  "Energy Efficient and Low-Cost Server Architecture for Hadoop Storage Appliance",
     Do Young Choi, Jung Hwan Oh, Ji Kwang Kim, and Seung Eun LEE,
     KSII Transactions on Internet and Information Systems (TIIS), Vol.14, No.12, pp.4648-4663, 2020.
  3.  "Design of a 128-bit AES Block Cipher Core",
     Jung Hwan Oh, Sang Muk Lee, Young Hyun Yoon and Seung Eun Lee,
     Journal of Integrated Circuits and Systems (JICAS), Vol.03, No.4, pp.41-46, 2017.
  2.  "Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression",
     Sang Muk Lee, Ji Hoon Jang, Jung Hwan Oh, Ji Kwang Kim and Seung Eun Lee,
      IEICE Electronics Express(ELEX), Vol.14, No.11, pp.20170399, May. 2017.
  1.  "Design of a DMA Controller for Loss-less Image Processing",
     Seong Mo Lee, Ji Hoon Jang, Sang Muk Lee, Jung Hwan Oh, and Seung Eun Lee,
      Journal of Integrated Circuits and Systems (JICAS), Vol.02, No.2, pp.1-6, 2016.

International Conference Papers
  10.  "An FPGA-based Electronic Control Unit Controller for Automotive Systems",
     Jung Hwan Oh, Yoon Young Hyun, Ji Kwang Kim, Hyung Bin Ihm, Shin Hye Jeon, Tae Heon Kim, and Seung Eun LEE
     International Conference on Consumer Electronics (ICCE2019)), Accepted.
  9.  "Remote In-System Reconfiguration for Automotive Device",
      Yoon Young Hyun, Jung Hwan Oh, Ji Kwang Kim, Hyung Bin Ihm, Shin Hye Jeon, Tae Heon Kim, and Seung Eun LEE
     International Conference on Consumer Electronics (ICCE2019)), Accepted.
  8.  "2D Line Draw Hardware Accelerator for Tiny Embedded Systems",
     Ji Kwang Kim, Jung Hwan Oh, Jun Hyeok Yang, and Seung Eun LEE
     International Conference on Consumer Electronics (ICCE2019)), Accepted.
  7.  "Real-time PPG Monitoring System for Mobile Healthcare Devices",
      Ji Kwang Kim, Jung Hwan Oh, Ohseong Gwon, Jung Wung Yang, and Seung Eun LEE
      21st International Symposium on Consumer Electronics (ISCE 2017), Kuala Lumpur, Malaysia, Nov. 2017.
  6.  "Design of CAN - CAN FD Bridge for In-Vehicle Network",
      Jung Hwan Oh, Jong Uk Wi, and Seung Eun Lee,
      14th International SoC Design Conference (ISOCC 2017), Seoul, Korea, Nov. 2017.
  5.  "In-Vehicle CAN FD Network Controller for Smart Wearable Devices",
     Jung Woo Shin, Jung Hwan Oh, Sang Muk Lee, Jae Jin Ko, Sang Yub Lee, and Seung Eun Lee,
      35th IEEE International Conference on Consumer Electronics (ICCE 2017), Las Vegas, Nevada, USA, Jan. 2017.
  4.  "CAN FD Controller for In-Vehicle System",
     Jung Woo Shin, Jung Hwan Oh, Sang Muk Lee, and Seung Eun Lee,
      13th International SoC Design Conference (ISOCC 2016), Jeju, Oct. 2016.
  3.  "Live Demonstration : CAN FD Platform for In-Vehicle Network",
     Jung Woo Shin, Jung Hwan Oh, Sang Muk Lee, and Seung Eun Lee,
      13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju, Oct. 2016.
  2.  "Live Demonstration : An FPGA based Hardware Compression Accelerator for Hadoop System",
     Sang Muk Lee, Jung Hwan Oh, Ji Hoon Jang, Seong Mo Lee, and Seung Eun Lee,
      13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju, Oct. 2016.
  1.  "Accelerating JPEG Image Compression for Audio Video Bridging",
     Jung Woo Shin, Jung Hwan Oh, Ji Hoon Jang, Sang Muk Lee, and Seung Eun Lee,
      13th International SoC Design Conference (ISOCC 2016), Jeju, Oct. 2016.

Korean Conference Papers
  5. "차량 전장 제어를 위한 FPGA 기반 저전력 고속 직렬 통신 컨트롤러 설계",
  오정환, 윤영현, 임형빈, 전신혜, 이승은
   2018년 대한전자공학회 하계종합학술대회, 2018년 6월.
  4. "모바일 기기를 위한 JPEG 하드웨어 인코딩 가속기 설계",
  이재원, 김지광, 오정환, 신정우, 이승은
  2017년 대한전자공학회 하계종합학술대회, 2017 7월.
  3. "차량용 CAN - CAN FD 통신을 위한 브릿지 구현",
  오정환, 이승은
  2017년 SoC 학술대회, 2017 5월.
  2. "멀티코어 프로세서를 위한 128비트 AES 암호화 코어",
  오정환, 이상묵, 이승은
  2016년 SoC 학술대회, 2016 5월.
  1. "웨어러블 디바이스를 위한 차량용 통신 네트워크 구현",
  신정우, 이상묵, 권오성, 오정환, 고재진, 이상엽 이승은
  2016년 SoC 학술대회, 2016 5월.

Chip Design Contest
  7.  "A Hardware Accelerator for Lempel-Ziv 4 (LZ4) Compression",
     Sang Muk Lee, Jung Hwan Oh, and Seung Eun Lee,
      14th International SoC Design Conference (ISOCC CDC 2017), Seoul, Korea, Nov. 2017.
  6.  "Design of A Low-power Processor for Internet of Things",
     Oh Seong Gwon, Jung Hwan Oh, Jae won Lee, and Seung Eun Lee,
      14th International SoC Design Conference (ISOCC CDC 2017), Seoul, Korea, Nov. 2017.
  5.  "Design of a CAN FD controller for In-Vehicle Infotainment System",
     Jung Woo Shin, Jung Hwan Oh, Jong Uk Wi, and Seung Eun Lee,
      14th International SoC Design Conference (ISOCC CDC 2017), Seoul, Korea, Nov. 2017.
  4.  "A 128-bit AES Block Cipher Core with Three Operation Modes",
     Sang Muk Lee, Jung Hwan Oh, and Seung Eun Lee,
      14th International SoC Design Conference (ISOCC CDC 2017), Seoul, Korea, Nov. 2017.
  3.  "A 128-bit AES Block Cipher Core with Three Operation Modes",
     Jung Hwan Oh, Sang Muk Lee, and Seung Eun Lee,
      14th International SoC Design Conference (ISOCC CDC 2017), Seoul, Korea, Nov. 2017.
  2.  "A DMA Controller for Loss-less Image Processing",
     Jung Hwan Oh, Seong Mo Lee, Ji Hoon Jang, Sang Muk Lee, and Seung Eun Lee,
      13th International SoC Design Conference (ISOCC 2016), Jeju, Oct. 2016.
  1.  "A LZ4 Compression Acceleration Engine",
     Jung Hwan Oh, Ji Hoon Jang, and Seung Eun Lee,
      13th International SoC Design Conference (ISOCC 2016), Jeju, Oct. 2016.

  [Presentations]
  4."Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing",Seoultech, Dec. 2017.
  3."FTL Design Exploration in Reconfigurable High-Performance SSD (RHPSSD) for Server Applications",Seoultech, Oct. 2017.
  2."Master Coursework Summary ", Seoultech, Oct. 2017.
  1."Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation ",SPL meeting, Aug. 2015.

  [Awards]
   2018.08.05-11. KSIA - 인피니언 연계 자동차용 반도체 전문인력 양성 교육 과정 우수

  [Skills]
   - FPGA Prototyping, ASIC Design
   - High-level Computer Language: C Programing, JAVA
   - Analysis Language: MATLAB
   - EDA tools: ModelSim, ORCAD Pspice, QuartusII, Xilinx ISE, Xilinx Vivado, IC Compiler, Design Compiler, Astro, VCS, NCsim, PrimeTime

  [Training]
   2018.01.10-01.11 - Deep Learning: 이해와 응용 (TensorFlow, Darknet, Tiny-DNN), IDEC.
   2017.08.21-09.01 - 인피니언 연계 자동차용 반도체 전문인력 양성과정[심화], KSIA, Infineon.
   2017.08.09-08.11 - Xilinx ZYNQ Device 설계 교육, IDEC.
   2017.07.03-07.14 - 인피니언 연계 자동차용 반도체 전문인력 양성과정[기본], KSIA, Infineon.
   2017.03.23 - 반도체 기반 IoT 플랫폼(삼성 IoT 플랫폼 ARTIK 활용), IDEC.
   2017.03.08-03.09 - OrCAD (Allegro) PCB를 이용한 PCB 설계, IDEC.
   2017.02.14-02.15 - [IDEC 연구원 교육]MS180 Digital Layout 설계 방법, IDEC.
   2017.02.07-02.09 - 기가비트 이더넷 제어기 설계와 응용설계, IDEC.
   2017.01.02-01.06 - MPW Design training, IDEC.
   2016.08.16-08.19 - Cortex_M0 DesignStart 기반의 SoC플랫폼 구성 및 활용, IDEC.
   2016.08.01-08.03 - IC Compiler 사용법 및 활용예, IDEC.
   2016.07.11-07.14 - 스마트 모바일 AP기반 SoC구조 및 주변장치 응용, IDEC.
   2016.07.04-07.07 - 지능형 웨어러블 시스템 설계, IDEC.
   2016.05.24 - 삼성 65nm 설계설명회, IDEC.
   2016.02.25 - Education for EISC development environment, ADChips.
   2016.01.12-01.15 - Verilog HDL 이론및 응용, IDEC.
   2015.12.28 - Zynq-Z7020 기반 SoC 설계, HUINS.
   2015.09.7-09.10 - MPW Design training, IDEC.
   2015.08.24-08.25 - 디지털 신호처리를 위한 고성능 SoC 설계, IDEC.
   2015.08.20 - 매그나칩/SK하이닉스 0.35um 설계설명회, IDEC.
   2015.08.18-08.20 - 안드로이드 플랫폼 개발과정 (리눅스 포팅, 디바이스 드라이버, 안드로이드 빌드), HUINS.
   2015.08.13 - 창의설계 코딩 기법 교육, HUINS.
   2015.07.06-07.08 - Full-custom 설계 입문, IDEC.

  [Graduate Courses]
   VLSI for Digital Signal Processing, Semiconductor Integrated Circuit Design II, Speech and Audio Processing,
   Computer Applied Circuit Design, Embedded Software, Advanced Computer Architecture,
   Special topic in Network-on-Chip, Advanced Digital Signal Processing,
   SoC Design Methodology, Master Thesis I/II

  [Undergraduate Courses]
   Computer Programming(C Programming), Digital Logic Circuit, Electromagnetics, Engineering Circuit Analysis,
   Electrical and Electronic Experiments, Engineering Mathmatics, Signals and Systems, Semiconductor Engineering,
   Microwave Engineering, Computer Application System Design, Electronic Circuits, Microprocessor,
   Mobile Programming, Advanced Semiconductor Devices, Computer Architecture, Application of Microprocessor,
   Digital Signal Processing and Applications, Image Processing, Internet Protocol, Communication System, Capstone Design(1),
   Mobile Communications Engineering, Embedded System, Capstone Design(2)

  [Chips]

9. "CAN FD Controller Based on ISO-11898:2015"

   - Designer : Yoon Young Hyun, Oh Jung Hwan, Yang Jun Hyeok
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2018. 7. 23
   - Power Supply : 3.3V
   - Core Size : 3.8mm x 3.8mm

8. "Programmable Finger Gesture Recognition based on k-nearest neighbors algorithm"

   - Designer : Kim Ji Kwang, Oh Jung Hwan
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2017. 9. 18
   - Power Supply : 3.3V
   - Core Size : 3.8mm x 3.8mm

7. "Low-power hardware accelerator for Biomedical Signal Processing"

   - Designer : Kim Ji Kwang, Gwon Oh Sung, Oh Jung Hwan
   - Technology : SMIC 0.11um CMOS (1-poly 6-metal)
   - Tape Out : 2017. 9. 11
   - Digital Power Supply : 1.2V
   - Analog Supply Voltage : 3.3V
   - Core Size : 3.5mm x 3.5mm

6. "CAN FD Controller for In-Vehicle Network Communication"

   - Designer : Oh Jung Hwan, Yang Jun Hyeok, Yoon Young Hyun
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2017. 5. 22
   - Power Supply : 3.3V
   - Core Size : 3.7mm x 3.7mm

5. "In-Vehicle Communication Network CAN FD for Wearable Devices"

   - Designer : Shin Jung Woo, Lee Sang Muk, Oh Jung Hwan
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2016. 9. 19
   - Power Supply : 3.3V
   - Core Size : 3.8mm x 3.8mm

4. "LZ4 Compression Hardware Accelerator"

   - Designer : Lee Sang Muk, Oh Jung Hwan
   - Technology : Samsung 65nm CMOSRF (1-poly 8-metal)
   - Tape Out : 2016. 8. 1
   - Power Supply : 3.3V
   - Core Size : 4mm x 4mm

3. "Multi-purpose Controllers for Subminiature Sensor Embedded in Wearable Device"

   - Designer : Kim Ji Kwang, Oh Jung Hwan
   - Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
   - Tape Out : 2016. 6. 13
   - Power Supply : 3.3V
   - Core Size : 5mm x 4mm

2. "128-bit AES Block Cipher Core for Three Operation Mode"

   - Designer : Lee Sang Muk, Oh Jung Hwan
   - Technology : Magnachip hynix 0.18um CMOS (1-poly 6-metal)
   - Tape Out : 2016. 5. 16
   - Power Supply : 3.3V
   - Core Size : 3.8mm x 3.8mm

1. "Accelerating JPEG Image Compression Engine"

   - Designer : Shin Jung Woo, Lee Sang Muk, Oh Jung Hwan
   - Technology : Magnachip hynix 0.35um CMOS (2-poly 4-metal)
   - Tape Out : 2016. 1. 11
   - Power Supply : 3.3V
   - Core Size : 5mm x 4mm
   - Operating Frequency : 28MHz

Computer Architecture Laboratory