서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
    2022.07 - present, Research Assistant, CAL Lab, Seoul National University of Science and Technology.
    2024.02 - present, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2019.03 - 2024.02, Undergraduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2017.03 - 2019.02, Undergraduate Student, Dept. of Energy Engineering, Dankook University.

  [Research Interests]
    Hardware Architecture for Neural Processing, Computer Architecture, Embedded System, System-on-Chip Design, Memory-Centric Computing, VLSI Implementation, Parallel Processing
  [Projects]
   - Next-Generation System Semiconductor Design Engineer Development Program
     Ministry of Trade, Industry and Energy, Korea (2024 - 2025)
   - Development of real time monitoring sensor for gas pipe
     Ministry of Trade, Industry and Energy, Korea (2023 - 2025)
   - Development for Processing Software on AI Semiconductor Devices
     Ministry of Science and ICT, Korea (2022 - 2025)
   - Development of DRAM PIM semiconductor technology for enhanced computing function for edge
     Ministry of Science and ICT, Korea (2022 - 2025)
   - ECC for high-speed SCM based PIM
     Korea Electronics Technology Institute, Korea (2022 - 2024)
   - Developed proximity/healthcare convergence sensor SoC for TWS (True Wireless Stereo)
     Ministry of Trade, Industry and Energy, Korea (2021 - 2023)

  [Publications]
  International Journal Papers
  9.    "Real-Time True Wireless Stereo Wearing Detection Using a PPG Sensor with Edge AI"
      Raehyeong Kim, Joungmin Park, Jaeseong Kim, Jongwon Oh, and Seung Eun Lee
      MDPI Electronics, vol. 14, no. 19, Sep. 2025
  8.    "An Accelerated Block Searching Approach in A* for Autonomous Mobile Robots"
      Jinyoung Shin, Joungmin Park, Jinyeol Kim, Yue Ri Jeong, Seongmo An, and Seung Eun Lee
      International Transaction on Circuits and Systems I: Regular Papers (TCAS-I), Jul. 2025.
  7.    "Hardware Accelerator for Approximation-Based Softmax and Layer Normalization in Transformers"
      Raehyeong Kim, Dayoung Lee, Jinyeol Kim, Joungmin Park, and Seung Eun Lee
      MDPI Electronics, vol. 14, no. 12, Jun. 2025
  6.    "SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources"
      Youngwoo Jeong, Joungmin Park, Raehyeong Kim, and Seung Eun Lee
      ELSEVIER Integration, vol. 101, Mar. 2025
  5.    "Grid-Based DBSCAN Clustering Accelerator for LiDAR’s Point Cloud"
      Sangho Lee, Seongmo An, Jinyeol Kim, Hun Namkung, Joungmin Park ,Raehyeong Kim, and Seung Eun Lee
      MDPI Electronics, vol. 13, no. 17, Aug. 2024
  4.    "DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting"
      Hyun Woo oh, Joungmin Park, and Seung Eun Lee
      IEEE Transactions on circuits and systems II: Express briefs (TCAS-II), vol. 71, no. 5, May. 2024
  3.    "Accelerating Strawberry Ripeness Classification Using a Convolution-Based Feature Extractor along with an Edge AI Processor"
      Joungmin Park, Jinyoung Shin, Raehyeong, Kim, Seongmo An, Sangho Lee, Jinyeol Kim, Jongwon Oh, Youngwoo Jeong, Soohee, Kim, Yue Ri Jeong, and Seung Eun Lee,
      MDPI Electronics, vol. 13, no. 2, Jan. 2024
  2.    "Intelligent Monitoring System with Privacy Preservation based on Edge AI"
      Soohee Kim, Joungmin Park, Youngwoo Jeong, and Seung Eun Lee,
      MDPI Micromachines, vol. 14, no. 9, Sep. 2023.
  1.    "Photoplethysmography-Based Distance Estimation for True Wireless Stereo",
      Youngwoo Jeong, Joungmin Park, Sun Beom Kwon, and Seung Eun Lee,
      MDPI Micromachines, vol. 14, no. 2, Jan. 2023.

  International Conference Papers
  2.    "Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture"
      Joungmin Park, Seongmo An, Jinyeol Kim, and Seung Eun Lee
      International SoC Design Conference (ISOCC 2023), Jeju, Korea, Oct. 2023.
  1.    "Embedded Monitoring System for Preventing Lonely Death Based on Edge AI"
      Soohee Kim, Joungmin Park, Young Woo Jeong, and Seung Eun Lee
      International Conference on Consumer Electronics (ICCE 2023), Las Vegas, USA, Jan. 2023.

  Korean Conference Papers
  7.    "Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor"
      Chaebin Lee, Jaeseong Kim, Dayoung Lee, Seongmo An, Joungmin Park, and Seung Eun Lee
      Korean Association Data Science (KADS), Spring Joint Academic Conference, Yeosu, Korea, May. 2025.
  6.    "Analysis of Numeric Formats in Artificial Intelligence Balancing Accuracy and Resource Usage in Depth-Wise Convolutions"
      Dayoung Lee, Jaeseong Kim, Chaebin Lee, Joungmin Park, Raehyeong Kim, and Seung Eun Lee
      The 32nd Korean Conference on Semiconductors (KCS), Gangwon, Korea, Feb. 2025.
  5.    "Analysis of Model Lightweighting Effects on Korean-English Machine Translation using Transformer"
      Raehyeong Kim, Jinyeol Kim, Joungmin Park, Yue Ri Jeong, and Seung Eun Lee
      Institute of Electronics and Information Engineers (IEIE), Summer Annual Conference, Jeju, Korea, June. 2024.
  4.    "CNN Preprocessing Based Embedded AI Strawberry Classifier"
      Jinyeol Kim, Jongwon Oh, Joungmin Park, and Seung Eun Lee,
      The 31st Korean Conference on Semiconductors (KCS), Gyeongju, Korea, Jan. 2024.
  3.    "TWS Wearing Detection System based on PPG Sensor using Embedded AI"
      Raehyeong Kim, Joungmin Park, Youngwoo Jeong, and Seung Eun Lee
      Institute of Semiconductor Engineers (ISE), The 6th General Conference, Seoul, Korea, Dec. 2023.
  2.    "Matrix Computation Accelerator based on Systolic Array for Convolution Processing"
      Joungmin Park, Raehyeong Kim, and Seung Eun Lee
      Institute of Electronics and Information Engineers (IEIE), Summer Annual Conference, Seoul, Korea, June. 2023.
  1.    "Library Management System based on Embedded AI Accelerator"
      Joungmin Park, Seong Mo An, Youngwoo Jeong, and Seung Eun Lee
      Institute of Semiconductor Engineers (ISE), The 5th General Conference, Seoul, Korea, Dec. 2022.

  [Workshop]
  1.    "JPS Accelerator Based Global Path Planning Processor for Autonomous Mobile Robots",
      Jinyoung Shin, Joungmin Park, Jinyeol Kim, Yue Ri Jeong, and Seung Eun Lee
      2nd Workshop on Robotics Acceleration with Computing Hardware (RoboARCH), Toronto, Canada, Oct. 2023.
      (Co-located with the IEEE/ACM International Symposium on Microarchitecture (MICRO))

  [Presentations]
  4.   "Configurable End-toEnd CNN Accelerator for Real-Time Age Estimation on FPGA", "[View]"
     김래형, 박정민 이승은,
     반도체공학회 하계종합학술대회, Live 데모 경진대회, Jul.2025.
  3.   "Multi-Stage Scalable Convolution-based Feature Extractor for the Memory-Centric Computing", "[View]"
     Joungmin Park, Seong Mo An and Seung Eun Lee,
     IEEE Seoul Section Student Paper Contest, Dec.2024.
  2.   "확장 가능한 임베디드 AI 시스템", "[View]"
     박정민, 안성모, 이상호, 이승은,
     일상에 스며드는 디지털 혁신, ICT Challenge 2024, Sep.2024.
  1.   "합성곱 가속기를 이용한 AI 시스템 반도체", "[View]"
     박정민, 김래형, 신진영, 김수희, 이승은,
     디지털로 펼쳐갈 미래로의 도전, ICT Challenge 2023, Sep.2023.

  [Awards]
   2025.07.15. 반도체공학회 하계종합학술대회 Live 데모 경진대회 - 우수상
      Topic: Configurable End-toEnd CNN Accelerator for Real-Time Age Estimation on FPGA
      반도체공학회 하계종합학술대회
   2025.06.13. The Spring Annual Conference of the Korean Data Science Society - Honorable Mention Award
      Topic: Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor
      The Institute of Korean Data Science Society
   2024.12.07. IEEE Seoul Section Student Paper Contest - Bronze Award
      Topic: Multi-Stage Scalable Convolution-based Feature Extractor for the Memory-Centric Computing
      IEEE Seoul Section Best Student Paper

  [Registered Copyright]
Patents
  1.   Method and Apparatus for Classifying Images
      Application No. PCT/KR2024/019962, Dec.2024, (PCT Patent Pending)
      Application No. 10-2024-0167572, Nov.2024, (Korea Patent Pending)
Software
  2.    광혈류 측정법을 이용한 TWS(티더블유에스) 착용감지 프로그램(program)
      Registration No.C-2024-049980, Dec, 2024, Korea (right owned by SeoulTech)
  1.    인공지능 가속기 성능 최적화를 위한 명령어 디코더 (decoder)
      Registration No.C-2024-047139, Dec, 2024, Korea (right owned by SeoulTech)

  [Skills]
    - Hardware Description Language: Verilog-HDL
    - High-level Programming Language: C/C++, Python
    - Analysis Language: System Verilog
    - FPGA Design Tools: Vivado, Quartus II, ModelSim
    - EDA Tools: Design Compiler, IC Compiler II, PrimeTime, VCS, Verdi, Formality, StarRC, Calibre DRC/LVS, Virtuoso Layout Suite

  [Training]
    2025.09.17-09.19 [IDEC, Synopsys] IC Compiler II를 활용한 Block-level Auto P&R
    2025.07.07-07.08 [IDEC, Siemens EDA] CUDA 기반 GPU 프로그래밍 기초
    2025.06.16-06.17 [IDEC, Siemens EDA] C/C++알고리즘 디자인으로부터 Verilog RTL을 구현/생성할 수 있는 Catapult High Level Synthesis 교육
    2025.05.28-06.01 [IDEC] AMD Xilinx FPGA HW 구성 이해 및 설계
    2025.04.10-04.11 [IDEC, Synopsys] 반도체 Logic설계 시뮬레이션 & 효율적인 디버깅 방법론을 위한 VCS/Verdi Training
    2025.01.08-01.10 [IDEC] Cell-Based Chip Design Front-End 교육(칩설계)
    2025.01.06-01.07 [IDEC] 인공지능 기초 및 AI 반도체 구조
    2024.05.30-05.31 [IDEC] AMBA AXI와 AXI-Stream 설계와 검증
    2023.08.07-08.09 [IDEC, Synopsys] SystemVerilog 검증 환경 만들기
    2023.05.15-05.19 [IDEC] Cell-Based Chip Design Flow 교육
    2023.04.24-04.25 [IDEC, Siemens EDA] C/C++알고리즘 디자인으로부터 Verilog RTL을 구현/생성할 수 있는 Catapult High Level Synthesis 교육
    2023.02.16-02.16 [IDEC] 인공지능 가속 프로세서
    2023.02.06-02.10 [KIRD] Basic Semiconductor Design Curriculum - PCB Artwork with OrCAD PCB Editor(Allegro)
    2022.11.28-11.29 [IDEC] 인공지능반도체 설계: Deep-Learning Processing Unit Design and Implementation
    2022.08.16-08.25 [KSIA, Infineon] 인피니언 연계 차량용 반도체 전문인력 양성과정(심화과정)
    2022.08.08-08.10 [KSIA, Infineon] 인피니언 연계 차량용 반도체 전문인력 양성과정(기본과정)
    2022.02.24-02.24 [IDEC] GPU 아키텍쳐와 CUDA 프로그래밍 모델
    2022.02.07-02.09 [IDEC] Intel FPGA를 이용한 Verilog
    2022.01.12-01.13 [IDEC] 임베디드 프로세서 구조의 이해
    2022.01.05-01.06 [IDEC] Computer arithmetic and VLSI signal Processing
    2021.12.27-12.28 [IDEC] 디지털 SoC 구조
    2021.12.01-12.02 [IDEC] 인공지능반도체(DPU) 설계
    2021.11.22-11.23 [IDEC] GPU 하드웨어 구조 및 활용

  [Courses]
    Digital System Design, Computer Programming(C Programming),
    Engineering Mathmatics, Computer Programming, Electromagnetics,
    Electronic Circuits, Logic Circuit, Semiconductor Engineering,
    Microprocessors Design, Machine Learning,
    Circuit Theory, Signal System, Mobile Communication Engineering,
    Computer Architecture, Mobile Programming(Java Programming)

  [Chips]

4. "A Reconfigurable AI Processor Executing Lightweight Algorithms for Sequential Data Applications"

    Designer: Raehyeong Kim, Jinyoung Shin, Jinyeol Kim, Dayoung Lee, Joungmin Park and Seung Eun Lee
    Technology: Samsung 28nm FD-SOI (1-Poly 10-Metal)
    Tape Out: 2025. 09. 25
    Operation Voltages: 1.1V/1.8V (Core/IO)
    Clock Frequency: 100MHz (max)
    Gate Counts: 360K @ 100MHz
    Memory Size: 8Kb*256 (AI region)
    Core Size: 4mm x 4mm

3. "A Networked Processor Array based on Heterogeneous Computing Units for AI Acceleration"

    Designer: Seongmo Ahn, Joungmin Park, Jongwon Oh, Jaeseong Kim and Seung Eun Lee
    Technology: Samsung 28nm LPP (1-Poly 10-Metal)
    Tape Out: 2025. 07. 07
    Operation Voltages: 1.0V/1.8V (Core/IO)
    Clock Frequency: 100MHz (max)
    Gate Counts: 468K @ 100MHz
    Memory Size: 8Kb*4/8Kb*4/128Kb*4 (Code/Data/AI region)
    Core Size: 4mm x 4mm

2. "A Internal Network IP for Next-Generation Robots with SPI"

    Designer: kwanghyun Go, Joungmin Park, Jongwon Oh
    Technology: DBHitek 180nm BCDMOS
    Tape Out: 2024. 07. 22
    Operation Voltages: 5.0V/1.8V (Core/IO)
    Clock Frequency: 50MHz (max)
    Gate Counts: 36K @ 50MHz
    Core Size: 5mm x 2.5mm

1. "CoFEx : Convolution-based Feature Extractor Equipped with an Improved Systolic Array Architecture"

    Designer: Joungmin Park, Sangho Lee, Jinyoung Shin, Raegyeong Kim and Seung Eun Lee
    Technology: Samsung 28nm LPP (1-Poly 10-Metal)
    Tape Out: 2024.07.18
    Operation Voltages: 1.0V/1.8V (Core/IO)
    Clock Frequency: 50MHz (max)
    Gate Counts: 245K @ 50MHz
    Memory Size: 512Kb (AI region)
    Core Size: 4mm x 4mm

Computer Architecture Laboratory