서울과학기술대학교 컴퓨터구조연구실

  [Education & Experiences]
    2022.07 - present, Research Assistant, CAL Lab, Seoul National University of Science and Technology.
    2024.02 - present, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2019.03 - 2024.02, Undergraduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
    2017.03 - 2019.02, Undergraduate Student, Dept. of Energy Engineering, Dankook University.

  [Research Interests]
    Hardware Architecture for Neural Processing
    VLSI Implementation for HW Acceleration for Neural Processing
    Memory-Centric Data Processing Architecture
    Computer Architecture
    Digital System Design

  [Projects]
   - Development of real time monitoring sensor for gas pipe,
   Ministry of Trade, Industry and Energy, Korea, 2022-2026.
   - Development of DRAM PIM semiconductor technology for enhanced computing function for edge,
   Ministry of Science and ICT, Korea, 2022-2025.
   - ECC for high-speed SCM based PIM,
   Korea Electronics Technology Institute, Korea, 2022-2025.
   - Development for Processing Software on AI Semiconductor Devices,
  Ministry of Science and ICT, Korea, 2022-2029.
   - Next-Generation System Semiconductor Design Engineer Development Program,
  Ministry of Trade, Industry and Energy, Korea, 2021-2026.
   - Developed proximity/healthcare convergence sensor SoC for TWS (True Wireless Stereo),
  Ministry of Trade, Industry and Energy, Korea, 2021-2023.

  [Publications]
  International Journal Papers
  7.    "An Accelerated Block Searching Approach in A* for Autonomous Mobile Robots",
      Jinyoung Shin, Joungmin Park, Jinyeol Kim, Yue Ri Jeong, Seongmo An, and Seung Eun Lee,
      International Transaction on Circuits and Systems I (TCAS-I), July. 2025.
  6.    "SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources",
      Youngwoo Jeong, Joungmin Park, Raehyeong Kim, and Seung Eun Lee,
      ELSEVIER Integration, vol. 101, no.102337, Mar. 2025
  5.    "Grid-Based DBSCAN Clustering Accelerator for LiDAR’s Point Cloud",
     Sangho Lee, Seongmo An, Jinyeol Kim, Hun Namkung, Joungmin Park ,Raehyeong Kim, and Seung Eun Lee,
     MDPI Electronics, vol. 13, no. 3395, Aug. 2024
  4.    "DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting",
     Hyun Woo oh, Joungmin Park, and Seung Eun Lee,
     IEEE Transactions on circuits and systems II: Express briefs (TCAS-II), vol. 13, no. 344, Jan. 2024
  3.    "Accelerating Strawberry Ripeness Classification Using a Convolution-Based Feature Extractor along with an Edge AI Processor",
     Joungmin Park, Jinyoung Shin, Raehyeong Kim, Seongmo An, Sangho Lee, Jinyeol Kim, Jongwon Oh, Youngwoo Jeong, Soohee Kim, Yue Ri Jeong, and Seung Eun Lee,
     MDPI Electronics, vol. 13, no. 344, Jan. 2024
  2.    "Intelligent Monitoring System with Privacy Preservation based on Edge AI",
     Soohee Kim, Joungmin Park, Youngwoo Jeong, and Seung Eun Lee,
     MDPI Micromachines, vol. 14, no. 9, Sep. 2023.
  1.   "Photoplethysmography-Based Distance Estimation for True Wireless Stereo",
     Youngwoo Jeong, Joungmin Park, Sun Beom Kwon, and Seung Eun Lee,
     MDPI Micromachines, vol. 14, no. 252, Jan. 2023.

  International Conference Papers
  4.    "An Accelerated Block Searching Approach in A* for Autonomous Mobile Robots" ,
     Jinyoung Shin, Joungmin Park, Jinyeol Kim, Yue Ri Jeong, Seongmo An, and Seung Eun Lee,
     International Symposium on Circuits and Systems (ISCAS 2025), London, United Kingdom, May. 2025.
  3.    "JPS Accelerator Based Global Path Planning Processor for Autonomous Mobile Robots",
     Jinyoung Shin, Joungmin Park, Jinyeol Kim, Yue Ri Jeong, and Seung Eun Lee,
     2nd Workshop on Robotics Acceleration with Computing Hardware (Co-located with the IEEE/ACM International Symposium on Microarchitecture (MICRO 2023)), Toronto, Canada, Oct. 2023.
  2.    "Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture",
     Joungmin Park, Seongmo An, Jinyeol Kim, and Seung Eun Lee,
     International SoC Design Conference (ISOCC 2023), Jeju, Korea, Oct. 2023.
  1.    "Embedded Monitoring System for Preventing Lonely Death Based on Edge AI",
     Soohee Kim, Joungmin Park, Young Woo Jeong, and Seung Eun Lee,
     International Conference on Consumer Electronics (ICCE 2023), Las Vegas, USA, Jan. 2023.

  Korean Conference Papers
  6.    "Analysis of Numeric Formats in Artificial Intelligence Balancing Accuracy and Resource Usage in Depth-Wise Convolutions",
     Dayoung Lee, Jaeseong Kim, Chaebin Lee, Joungmin Park, Raehyeong Kim, and Seung Eun Lee
     The 32nd Korean Conference on Semiconductors (KCS), Gangwon, Korea, Feb. 2025.
  5.    "Analysis of Model Lightweighting Effects on Korean-English Machine Translation using Transformer",
     Raehyeong Kim, Jinyeol Kim, Joungmin Park, Yue Ri Jeong, and Seung Eun Lee
     Summer Annual Conference of IEIE, Jeju, Korea, June. 2024.
  4.    "CNN Preprocessing Based Embedded AI Strawberry Classifier",
     Jinyeol Kim, Jongwon Oh, Joungmin Park, and Seung Eun Lee,
     The 31st Korean Conference on Semiconductors (KCS), Gyeongju, Korea, Jan. 2024.
  3.    "TWS Wearing Detection System based on PPG Sensor using Embedded AI",
     Raehyeong Kim, Joungmin Park, Youngwoo Jeong, and Seung Eun Lee
     Institute of Semiconductor Engineering Conference (ISE), Seoul, Korea, Dec. 2023.
  2.    "Matrix Computation Accelerator based on Systolic Array for Convolution Processing",
     Joungmin Park, Raehyeong Kim and Seung Eun Lee,
     Summer Annual Conference of IEIE 2023, Seoul, Korea, June. 2023.
  1.    "Library Management System based on Embedded AI Accelerator",
     Joungmin Park, Seong Mo An, Youngwoo Jeong and Seung Eun Lee,
     Institue of Semiconductor Engineering Conference (ISE 2022), Seoul, Korea, Dec. 2022.

  [Presentations]
  4.  "Configurable End-toEnd CNN Accelerator for Real-Time Age Estimation on FPGA", "[View]"
     Raehyeong Kim, Joungmin Park and Seung Eun Lee,
     반도체공학회 하계종합학술대회, Live 데모 경진대회, Jul.2025.
  3.  "Multi-Stage Scalable Convolution-based Feature Extractor for the Memory-Centric Computing", "[View]"
     Joungmin Park, Seong Mo An and Seung Eun Lee,
     IEEE Seoul Section Student Paper Contest, Dec.2024.
  2.  "확장 가능한 임베디드 AI 시스템", "[View]"
     박정민, 안성모, 이상호, 이승은,
     일상에 스며드는 디지털 혁신, ICT Challenge 2024, Sep.2024.
  1.  "합성곱 가속기를 이용한 AI 시스템 반도체", "[View]"
     박정민, 김래형, 신진영, 김수희, 이승은,
     디지털로 펼쳐갈 미래로의 도전, ICT Challenge 2023, Sep.2023.

  [Awards]
  2025.07.15. 2025 반도체공학회 하계종합학술대회 Live 데모 경진대회 - 우수상
     Topic: Configurable End-toEnd CNN Accelerator for Real-Time Age Estimation on FPGA
     반도체공학회 하계종합학술대회
  2025.06.13. 2025 The Spring Annual Conference of the Korean Data Science Society - Honorable Mention Award
     Topic: Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor
     The Institute of Korean Data Science Society
  2024.12.07. 2024 IEEE Seoul Section Student Paper Contest - Bronze Award
     Topic: Multi-Stage Scalable Convolution-based Feature Extractor for the Memory-Centric Computing
     IEEE Seoul Section Best Student Paper

  [Registered Copyright]
Patents
  2.    Performance optimization technique utilizing hybrid model-based AI devices
      Application No. PCT/KR2024/019962, Dec.2024, PCT (right owned by SeoulTech)
  1.    이미지 분류 방법 및 장치
      Application No. 10-2024-0167572, Nov.2024, Korea (right owned by SeoulTech)
Software
  2.   광혈류 측정법을 이용한 TWS(티더블유에스) 착용감지 프로그램(program)
     Registration No.C-2024-049980, Dec, 2024, Korea (right owned by SeoulTech)
  1.   인공지능 가속기 성능 최적화를 위한 명령어 디코더 (decoder)
     Registration No.C-2024-049980, Dec, 2024, Korea (right owned by SeoulTech)

  [Skills]
    - High-level Programming Language: C/C++, Python
    - Hardware Description Language: Verilog HDL
    - Analysis Language: MATLAB
    - FPGA Design Tools: Vivado, Quartus II
    - EDA Tools: VCS, Verdi, ModelSim

  [Training]
    2023.08.07-08.09 [IDEC, Synopsys] Creating a SystemVerilog Verification Environment
    2023.05.15-05.19 [IDEC] Cell-Based Chip Design Flow Training for Samsung 28nm Technology
    2023.04.24-04.25 [IDEC, Siemens EDA] Catapult High Level Synthesis Training to Implement/Create Verilog RTL from C/C++ algorithm design
    2023.02.16-02.16 [IDEC] Artificial Intelligence Acceleration Processor
    2023.02.06-02.10 [KIRD] Basic Semiconductor Design Curriculum - PCB Artwork with OrCAD PCB Editor(Allegro)
    2022.11.28-11.29 [IDEC] Deep-Learning Processing Unit Design and Implementation
    2022.08.16-08.25 [Infineon] Professional Training Course for Automotive Semiconductor, Korea Semiconductor Industry Association
    2022.08.08-08.10 [Infineon] Basic Training Course for Automotive Semiconductor, Korea Semiconductor Industry Association
    2022.02.24-02.24 [IDEC] GPU architecture and the CUDA programming model
    2022.02.07-02.09 [IDEC] Verilog using Intel FPGA
    2022.01.12-01.13 [IDEC] Understanding Embedded Processor Architecture
    2022.01.05-01.06 [IDEC] Computer arithmetic and VLSI signal Processing
    2021.12.27-12.28 [IDEC] Digital SoC structure
    2021.12.01-12.02 [IDEC] Artificial Intelligence Semiconductor(DPU) Design
    2021.11.22-11.23 [IDEC] GPU Hardware Structure and Utilization

  [Courses]
    Digital System Design, Computer Programming(C Programming),
    Engineering Mathmatics, Computer Programming, Electromagnetics,
    Electronic Circuits, Logic Circuit, Semiconductor Engineering,
    Microprocessors Design, Machine Learning,
    Circuit Theory, Signal System, Mobile Communication Engineering,
    Computer Architecture, Mobile Programming(Java Programming)

  [Chips]

3. "A Networked Processor Array based on Heterogeneous Computing Units for AI Acceleration"

    Designer: Seongmo Ahn, Joungmin Park, Jongwon Oh, Jaeseong Kim and Seung Eun Lee
    Technology: Samsung 28nm LPP CMOS, 1-Poly 8-Metal
    Tape Out: 2025. 07. 07
    Power Supply: 1.2V
    Core Size: 4mm x 4mm
    Operating Frequency: 100MHz

2. "A Internal Network IP for Next-Generation Robots with SPI"

    Designer: kwanghyun Go, Soohee Kim,Joungmin Park, Jongwon Oh
    Technology: DBHitek 180nm BCDMOS, 1-Poly 6-Metal
    Tape Out: 2024. 12. 06
    Power Supply: 5V
    Core Size: 5mm x 2.5mm
    Operating Frequency: 50MHz

1. "CoFEx : Convolution-based Feature Extractor Equipped with an Improved Systolic Array Architecture"

    Designer: Joungmin Park, Sangho Lee, Jinyoung Shin, Raegyeong Kim and Seung Eun Lee
    Technology: Samsung 28nm LPP CMOS, 1-Poly 8-Metal
    Tape Out: 2024.07.18
    Power Supply: 1.2V
    Core Size: 4mm x 4mm
    Operating Frequency: 50MHz/200MHz

Computer Architecture Laboratory