Information Engineering
Seoul National University
of Science and Technology
232 Gongneung-ro, Nowon-gu,
01811, Seoul, KOREA
kimjaeseong
seoultech.ac.kr
Information Engineering
Seoul National University
of Science and Technology
232 Gongneung-ro, Nowon-gu,
01811, Seoul, KOREA
kimjaeseongseoultech.ac.kr2024.05 - present, Research Assistant, SoC Platform Lab, Seoul National University of Science and Technology.
2020.03 - present, Undergraduate Student, Dept. of Electronic, Seoul National University of Science and Technology.
Digital System Design
Processor Architecture
- Development of real time monitering sensor for gas pipe,
Ministry of Trade, Industry and Energy, Korea, 2022-2026.
- Development for Processing Software on AI Semiconductor Devices,
Ministry of Science and ICT, Korea, 2022-2029.
International Journal Papers
1. "Real-Time True Wireless Stereo Wearing Detection Using a PPG Sensor with Edge AI",
Raehyeong Kim, Joungmin Park, Jaeseong Kim, Jongwon Oh, and Seung Eun Lee,
Electronics, vol. 14, no. 19, Sep. 2025
Korean Conference Paper
3. "Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor",
Chabin Lee, Jaeseong Kim, Dayoung Lee, Seongmo An, Joungmin Park, and Seung Eun Lee
The Spring Annual Conference of the Korean Data Science Society, June. 2025
2. "FP8-FP16 혼합 정밀도 기반의 MobileNetV1 추론 성능 분석",
Jaeseong Kim, Chabin Lee, Dayoung Lee, and Seung Eun Lee
Summer Annual Conference of IEIE 2025, June. 2025
1. "Analysis of Numeric Formats in Artificial Intelligence Balancing Accuracy and Resource Usage in Depth-wise Convolutions",
Dayoung Lee, Jaeseong Kim, Chabin Lee, Joungmin Park, RaeHyeong Kim, and Seung Eun Lee
The 32nd Korean Conference on Semiconductors (KCS 2025), Feb. 2025
2025.06.13. 2025 The Spring Annual Conference of the Korean Data Science Society - Honorable Mention Award
Topic: Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor
The Institute of Korean Data Science Society
2025.01.23. 2024 AI Semiconductor Idea/Design Competition - Industrial-Academic Cooperation Group Award
Topic: RLC 알고리즘 기반 Depth-wise Convolution 연산 가속기
The Institute of Information & Communications Technology Planning & Evaluation
2024.12.11. 2024 Korea Student Semiconductor IC Desogm Contest - Silver Award
The Institute of Semiconductor Engineers
2024.10.24. The 25th Korean Semiconductor Design Competition - Corporate (Cadence) Special Award
Topic: Embedded system을 위한 하드웨어 WebAssembly 가속기
Korea Semiconductor Industry Association
- High-level Programming Language: Python
- Hardware Description Language: Verilog
- FPGA Design Tools: Quartus II
- EDA Tools: ModelSim
2025.06.16-01.17 [IDEC] [Siemens] C/C++알고리즘 디자인으로부터 Verilog RTL을 구현/생성할 수 있는 Catapult High Level Synthesis 교육
[IDEC] 2025.01.14-01.16 [IDEC] System Verilog를 이용한 검증 방법론
Digital System Design, Computer Architechture,
Logic Circuit, Micro Processor, Application of Micro Processor,
Control Engineering, Control Systems Engineering,
Computer Programming(C Programming), Mobile Programing,
Electronic Circuits, Electronic Circuits2, Signal System,
Engineering Mathmatics, Electromagnetics, Circuit Theory,
Microwave Engineering, Semiconductor Engineering
1. "A Networked Processor Array based on Heterogeneous Computing Units for AI Acceleration"
Designer: Seongmo Ahn, Joungmin Park, Jongwon Oh, Jaeseong Kim and Seung Eun Lee
Technology: Samsung 28nm LPP (1-Poly 10-Metal)
Tape Out: 2025. 07. 07
Operation Voltages: 1.0V/1.8V (Core/IO)
Clock Frequency: 100MHz (max)
Gate Counts: 468K @ 100MHz
Memory Size: 8Kb*4/8Kb*4/128Kb*4 (Code/Data/AI region)
Core Size: 4mm x 4mm
