Information Engineering
Seoul National University
of Science and Technology
232 Gongneung-ro, Nowon-gu,
01811, Seoul, KOREA
leedayoung
seoultech.ac.kr
Information Engineering
Seoul National University
of Science and Technology
232 Gongneung-ro, Nowon-gu,
01811, Seoul, KOREA
leedayoungseoultech.ac.kr2024.05 - present, Research Assistant, Computer Architecture Lab, Seoul National University of Science and Technology.
2022.03 - present, Undergraduate Student, Dept. of Electronic, Seoul National University of Science and Technology.
Processor Architecture
Deep Learning
Coarse Grained Reconfigurable Architecture
- Development of real time monitering sensor for gas pipe,
Ministry of Trade, Industry and Energy, Korea, 2022-2026.
- Development for Processing Software on AI Semiconductor Devices,
Ministry of Science and ICT, Korea, 2022-2029.
3. "Memory-Efficient Depthwise Convolution Accelerator with Run-Length Coding",
Chabin Lee, Jaeseong Kim, Dayoung Lee and Seung Eun Lee,
2025 International SoC Design Conference (ISOCC), Oct. 2025
2. "FPGA Based Approximate Vector Operation Accelerator for VLMs",
Raehyeong Kim, Chaebin Lee, Dayoung Lee, Yue Ri Jeong and Seung Eun Lee,
2024 International Conference on Electronics, Information, and Communication (ICEIC)), January. 2025.
1. "Flexible NTT/iNTT Accelerator Based on Montgomery Reduction",
Jinyeol Kim, Jinyoung Shin, Seongmo An, Chaebin Lee, Dayoung Lee and Seung Eun Lee,
2025 International Conference on Consumer Electornics (ICCE), Las Vegas, NV, USA, January. 2025.
Korean Conference Papers
2. "FP8-FP16 혼합 정밀도 기반의 MobileNetV1 추론 성능 분석",
Jaeseong Kim, Chaebin Lee, Dayoung Lee and Seung Eun Lee,
2025 The Institute of Electronics and Information Engineers, June. 2025.
1. "Analysis of Numeric Formats in Artificial Intelligence Balancing Accuracy and Resource Usage in Depth-Wise Convolutions",
Dayoung Lee, Jaeseong Kim, Chaebin Lee, Joungmin Park, Raehyeong Kim, and Seung Eun Lee
The 32nd Korean Conference on Semiconductors (KCS 2025), Feb. 2025.
Student Research Competition
1. "A Pipelined Multi-Bank GEMM Accelerator for Memory Bottleneck Mitigation", "[View]"
Dayoung Lee, Chaebin Lee, Jaeseong Kim, and Seung Eun Lee
ACM SRC @ International Conference on Parallel Architectures and Compilation Techniques 2025 (PACT 2025 SRC), Irvine, CA, USA, Nov. 2025.
2. A Pipelined Multi-Bank GEMM Accelerator for Memory Bottleneck Mitigation,
ACM SRC @ International Conference on Parallel Architectures and Compilation Techniques 2025 (PACT 2025 SRC), Irvine, CA, USA, Nov. 2025.
1. Analysis of Numeric Formats in Artificial Intelligence Balancing Accuracy and Resource Usage in Depth-Wise Convolutions,
The 32nd Korean Conference on Semiconductors (KCS 2025), Feb. 2025.
2025.11.06. ACM Student Research Competition (SRC) @ PACT 2025 - 2nd Place in Undergraduate Session
Topic: A Pipelined Multi-Bank GEMM Accelerator for Memory Bottleneck Mitigation
ACM SRC @ International Conference on Parallel Architectures and Compilation Techniques 2025
2025.06.13. 2025 The Spring Annual Conference of the Korean Data Science Society - Honorable Mention Award
Topic: Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor
The Institute of Korean Data Science Society
2025.01.23. 2024 AI Semiconductor Idea/Design Competition - Industrial-Academic Cooperation Group Award
Topic: RLC 알고리즘 기반 Depth-wise Convolution 연산 가속기
The Institute of Information & Communications Technology Planning & Evaluation
2024.12.11. 2024 Korea Student Semiconductor IC Design Contest - Cadence Award
Topic: 동형암호를 위한 Montgomery 기반 fully pipelined NTT/iNTT
The Institute of Semiconductor Engineers
- High-level Programming Language: Python
- Hardware Description Language: Verilog HDL
- FPGA Design Tools: Quartus II, Vivado
- EDA Tools: ModelSim, Vivado
2025.11.19 삼성 HBM-PIM 이론 및 실습
2025.07.07-07.08 [IDEC] Verilog HDL을 사용한 CNN의 FPGA 구현
2025.06.16-06.17 [IDEC] Catapult High Level Synthesis
2025.01.14-01.16 [IDEC] System Verilog
Operating System
Digital System Design, Computer Architecture, Machine Learining, Deep Learning, Data Structure and Algorithm
Computer Programming (C Programming), Engineering Mathmatics, Electrical and Electronic Experiment
Electromagnetics, Digital Logic Circuit, Signal and Systems, Circuit Theory
Electronic Circuits, Digital System Design, Machine Learning, Digital Signal Processing
1. "A Reconfigurable AI Processor Executing Lightweight Algorithms for Sequential Data Applications"
- Designer: Raehyeong Kim, Jinyoung Shin, Jinyeol Kim, Dayoung Lee, Joungmin Park and Seung Eun Lee
- Technology: Samsung 28nm FD-SOI
- Tape Out: 2025.09.25
- Power Supply: 1.1V / 1.8V
- Core Size: 4mm x 4mm
- Operating Frequency: 100MHz
