← Alumni
Gwanbeom Hwang

Gwanbeom Hwang (2020)

Dept. of Electronic and Information Engineering Seoul National University of Science and Technology
232 Gongneung-ro, Nowon-gu, 01811, Seoul, KOREA

Education & Experiences

Engineer, ABOV Semiconductor Co.
2020.08, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
- Thesis Title : "Embedded SoC Architecture Based on Hardware Accelerator"
2020.08, M.S. in Electronic Engineering, The Graduate School, Seoul National University of Science and Technology.
2018.03 - 2020.08, Research Assistant, SoC Platform Lab, Seoul National University of Science and Technology.
2016.02, B.S. in Electronic Engineering, Korea Polytech University.

Research Interests

SoC Design
Graphics Accelerator
Signal Processing Accelerator
Compression Accelerator

Projects

  1. 뉴로모픽 기반 임베디드 인공지능 모듈 및 시스템 기술 개발
    산업통상자원부, 2019-2021.
  2. 고성능컴퓨팅(HPC)을 위한 멀티코어 하드웨어 가속기 핵심 기술 개발
    과학기술정보통신부, 2019-2022.
  3. 저전력 독립운용이 가능한 내장형 인공지능 모듈 및 내비게이션 응용 서비스 기술 개발
    산업통상자원부, 2017-2020.
  4. 호흡치료기 디바이스용 경량 SW-SoC 솔루션 개발
    산업통상자원부, 2017-2020.

Publications

International Journals

  1. 3
  2. 2
  3. 1
    Design of Low-Power SoC for Wearable Healthcare Device
    Jikwang Kim, Junghwan Oh, Gwanbeom Hwang, Ohseong Gwon, Seung Eun LEE
    Journal of Circuits, Systems, and Computers (JCSC) · Vol. 29 · No. 6 · May 2020

Chips

2020

Implementation of Lossless Decompression Accelerator Based on Inflate Algorithm
Gwanbeom Hwang, Doyoung Choi, Hyunwoo Oh, Changyeop Han, Seung Eun LEE
Tech
Samsung 65nm RFCMOS (1-poly 8-metal)
Tape-out
2020.09.14
Core
4mm x 4mm
Power
1.2V
High-Speed automobile communication based on CAN-FD Controller
Doyoung Choi, Younghyun Yoon, Gwanbeom Hwang, Kwonneung Cho, Seung Eun LEE
Tech
TSMC 180nm BCDMOS
Tape-out
2020.05.13
Core
2.5mm x 5mm
Power
2.5V

2019

A Low Power AI Processor for Embedded System
Younghyun Yoon, Gwanbeom Hwang, Doyoung Choi, Seung Eun LEE
Tech
Samsung 65nm CMOSRF (1-poly 8-metal)
Tape-out
2019.09.16
Core
4mm x 4mm
Power
1.8V
A Low Power SoC for Digital Signal Processing in Embedded System
Gwanbeom Hwang, Younghyun Yoon, Changyeop Han, Seung Eun LEE
Tech
Magnachip hynix 0.18um CMOS
Tape-out
2019.06.17
Core
3.8mm x 3.8mm
Power
3.3V
A Low Power AI Processor for face expression recognition based on k-NN and RBF
Younghyun Yoon, Suyeon Jang, Changyeop Han, Gwanbeom Hwang, Seung Eun LEE
Tech
Magnachip hynix 0.35um CMOS
Tape-out
2019.01.14
Core
5mm x 4mm
Power
3.3V

Tech. Notes

5. Gwan Beom HWANG, "Inflate-Decompression_Guideline", Seoultech, Feb. 2020.
4. Gwan Beom HWANG, "Inflate-Decompression_UserManual", Seoultech, Feb. 2020.
3. Gwan Beom HWANG, "Integrated Circuits Trainning Material", Fall. 2019.
2. Gwan Beom HWANG, "Design Compiler tutorial", Seoultech, May. 2019.
1. Gwan Beom HWANG, "VCS Verilog Encryption", Seoultech, Oct. 2018.

Chip Design Contest

  • 1. "Design of a Programmable Finger Gesture Recognition System for Embedded Devices",
    Ji Kwang Kim, Jung Hwan Oh, Young Hyun Yoon, Gwan Beom Hwang, Su Yeon Jang, and Seung Eun Lee
    15th International SoC Design Conference (ISOCC 2018), Daegu NOV, 2018.

Presentations

  • 3. "Cortex-M0 Designstart 기반의 SoC 플랫폼 설계",Seoultech, Spring, 2019
  • 2. "2D Line Draw Hardware Accelerator for Tiny Embedded Systems",
    International Conference on Consumer Electronics (ICCE2019), Las Vegas, NV, USA, Jan. 2019.
  • 1. "Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling",CSL meeting, Dec, 2018

Skills

High-level programming language : C/C++
Hardware description language : Verilog
Analysis language : MATLAB
FPGA design tools : Synplify, Quartus II, Vivado
EDA tools : ModelSim, NCsim, VCS, Design Compiler, Astro, IC Compiler I/II
PCB design tools : ORCAD Pspice Designer, Allegro PCB Designer, PADS

Training

2019.05.28-05.30 - [Synopsys] IC Compiler II를 활용한 Block-level Auto P&R, IDEC.
2019.03.04-03.08 - [IDEC 연구원 교육] Cell-Based Chip Design Flow, IDEC.
2019.02.11-02.12 - Cortex-M0 DesignStart 기반의 SoC플랫폼 구성 및 활용, IDEC.
2019.01.21-01.31 - 인피니언 연계 자동차용 반도체 전문인력 양성과정(심화과정), KSIA.
2018.11.26-11.30 - [IDEC 연구원 교육] Cell-Based Chip Design Flow, IDEC.
2018.08.10-08.14 - Full-custom 설계 실습, IDEC.
2018.07.02-07.04 - 스마트 모바일 AP 구조 및 주변장치 응용, IDEC.

Courses

Computer Programming(C Programming), Digital Engineering and Hands-on, Engineering Mathmatics,
Electromagnetics, Electronic Circuits and Practice, Communication theory, Semiconductor Engineering,
Signals and Systems, VHDL and Hands-on, Microprocessor, Digital Communication, Circuits theory,
DSP System and Hands-on, Image Signal Processing Application, SoC Design and Hands-on