Dissertation

  • Design and Analysis of On-Chip Interconnection Network for Multi-Processor System-on-Chip
    University of California, Irvine, Dec. 2008.

Book

  • B.2
    Verilog HDL을 이용한 디지털 시스템 설계 Verilog HDL: Digital System Design Using Verilog HDL
    Seung Eun LEE, Kwangmoonkag, March 2020.

Book Chapter

  • B.1
    Chapter 9: Energy/Power Issues in Network-on-Chip (NoC)
    Seung Eun LEE and Nader Bagherzadeh, Network-on-Chips: Theory and Practice, CRC Press, March 2009.

International Journals

  1. 60
    A Memory-Efficient Depthwise Separable Convolution Accelerator Using Run-Length Coding
    Electronics · Vol. 15 · No. 17 · Aug. 2026
  2. 59
    Real-Time True Wireless Stereo Wearing Detection Using a PPG Sensor with Edge AI
    Electronics · Vol. 14 · No. 3911 · Sep. 2025
  3. 58
    An Accelerated Block Searching Approach in A* for Autonomous Mobile Robots
    IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) · Vol. 72 · pp. 7516-7528 · Jun. 2025
  4. 57
    A CRC Comparison-Based Screen Data Management for Energy Efficient Virtual Desktop Infrastructure
    IEEE Access · Vol. 13 · pp. 102859-102868 · Jul. 2025
  5. 56
    Hardware Accelerator for Approximation-Based Softmax and Layer Normalization in Transformers
    Electronics · Vol. 14 · No. 2337 · Apr. 2025
  6. 55
    SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources
    Integration-the VLSI Journal · Vol. 101 · No. 102337 · Mar. 2025
  7. 54
    PIMCoSim: HW/SW Co-Simulator for Exploring Processing-in-Memory
    Electronics · Vol. 13 · No. 4795 · Dec. 2024
  8. 53
    Hardware-Based WebAssembly Accelerator for Embedded System
    Electronics · Vol. 13 · No. 3979 · Oct. 2024
  9. 52
    Grid-Based DBSCAN Clustering Accelerator for LiDAR's Point Cloud
    Electronics · Vol. 13 · No. 3395 · Aug. 2024
  10. 51
    Lightweight and Error-Tolerant Stereo Matching with a Stochastic Computing Processor
    Electronics · Vol. 13 · No. 2024 · May 2024
  11. 50
    DL-Sort: A Hybrid Approach to Scalable Hardware-Accelerated Fully-Streaming Sorting
    IEEE Transactions on circuits and systems II: Express briefs (TCAS-II) · Vol. 71 · No. 5 · 2024
  12. 49
    Accelerating Strawberry Ripeness Classification Using a Convolution-Based Feature Extractor along with an Edge AI Processor
    Electronics · Vol. 13 · No. 344 · Jan. 2024
  13. 48
    Intelligent Monitoring System with Privacy Preservation based on Edge AI
    Micromachines · Vol. 14 · No. 9 · Sep. 2023
  14. 47
    The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension
    IEEE Access · Vol. 11 · pp. 49409-49421 · May 2023
  15. 46
    Parallel Stochastic Computing Architecture for Computationally Intensive Applications
    Electronics · Vol. 12 · No. 7 · Apr. 2023
  16. 45
    Photoplethysmography-Based Distance Estimation for True Wireless Stereo
    Micromachines · Vol. 14 · No. 2 · Jan. 2023
  17. 44
    An Edge AI Device based Intelligent Transportation System
    Journal of Information and Communication Convergence Engineering (JICCE) · Vol. 20 · No. 3 · Sep. 2022
  18. 43
    An FPGA-Based ECU for Remote Reconfiguration in Automotive Systems
    Micromachines · Vol. 12 · No. 1309 · Oct. 2021
  19. 42
    Simulation-Based Fault Analysis for Resilient System-On-Chip Design
    Journal of Information and Communication Convergence Engineering (JICCE) · Vol. 19 · No. 3 · pp. 175-179 · Sep. 2021
  20. 41
    A Multi-Core Controller for an Embedded AI System Supporting Parallel Recognition
    Micromachines · Vol. 12 · No. 852 · Jul. 2021
  21. 40
    ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator
    Micromachines · Vol. 12 · No. 838 · Jul. 2021
  22. 39
    The Design of a 2D Graphics Accelerator for Embedded Systems
    Electronics · Vol. 10 · No. 4 · Feb. 2021
  23. 38
    Lossless Decompression Accelerator for Embedded Processor with GUI
    Micromachines · Vol. 12 · No. 145 · Jan. 2021
  24. 37
    Energy Efficient and Low-Cost Server Architecture for Hadoop Storage Appliance
    KSII Transactions on Internet and Information Systems (TIIS) · Vol. 14 · No. 12 · pp. 4648-4663 · Dec. 2020
  25. 36
    Intellino: Processor for Embedded Artificial Intelligence
    Electronics · Vol. 9 · No. 1169 · Jul. 2020
  26. 35
    Design of Low-Power SoC for Wearable Healthcare Device
    Journal of Circuits, Systems, and Computers (JCSC) · Vol. 29 · No. 6 · May 2020
  27. 34
    Design of a 128-bit AES Block Cipher Core
    IDEC Journal of Integrated Circuits and Systems (JICAS) · Vol. 3 · No. 4 · pp. 41-46 · 2017
  28. 33
    Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression
    IEICE Electronics Express (ELEX) · Vol. 14 · No. 11 · pp. 20170399 · 2017
  29. 32
    Design of a DMA Controller for Loss-less Image Processing
    IDEC Journal of Integrated Circuits and Systems (JICAS) · Vol. 2 · No. 2 · pp. 1-6 · 2016
  30. 31
    Intra-body Communication Modem on FPGA with AHB-Lite Bus Interface
    Journal of Applied Science and Engineering (JASE) · Vol. 18 · No. 4 · pp. 381-385 · Dec. 2015
  31. 30
    3D Interaction Glove: Virtual and Physical Space Realization Through Data Glove
    International Journal of Applied Engineering Research (IJAER) · Vol. 10 · No. 17 · pp. 38354-38357 · Oct. 2015
  32. 29
    Sharing Computation Resources for Large-Scale Recognition System-on-Chip (SoC)
    International Journal of Applied Engineering Research (IJAER) · Vol. 10 · No. 17 · pp. 38066-38069 · Oct. 2015
  33. 28
    Survey of Fault-Injection Techniques for Resilient System-on-Chip Design
    International Journal of Applied Engineering Research (IJAER) · Vol. 10 · No. 17 · pp. 38377-38383 · Oct. 2015
  34. 27
    Little Core Based SoC Platform for Intern of Thing (IoT)
    International Journal of Electrical and Computer Engineering (IJECE) · Vol. 5 · No. 4 · pp. 695-700 · Aug. 2015
  35. 26
    A Scalable Large Format Display Based on Zero Client Processor
    International Journal of Electrical and Computer Engineering (IJECE) · Vol. 5 · No. 4 · pp. 714-719 · Aug. 2015
  36. 25
    Implementation of Smart U-Health Care System
    Yeongseob Jeong, Yeong Ju Kwon, Seung Eun LEE
    Information Journal · Vol. 17 · No. 10 · pp. 4911-49916 · (A) · Oct. 2014
  37. 24
    Image Acquisition and Pre-Processing System for Single Photon Counting X-Ray Imaging
    Sangdon Kim, Ki-Man jeon, Jae Gi Son, Seung Eun LEE
    Information Journal · Vol. 17 · No. 4 · Apr. 2014
  38. 23
    Deadlock-free XY-YX router for On-Chip Intertconnection Network
    IEICE Electronics Express (ELEX) · Vol. 10 · No. 20 · pp. 20130699 · Oct. 2013
  39. 22
    IPFM: Intelligent Pressure Foot-Mouse
    International Journal of Multimedia and Ubiquitous Engineering (IJMUE) · Vol. 8 · No. 5 · pp. 31-40 · Sep. 2013
  40. 21
    Multi-Energy X-Ray Imaging System Using Single Photon Counting
    International Review on Computers and Software · Vol. 8 · No. 7 · pp. 1517-1521 · Jul. 2013
  41. 20
    Environment for Single Photon Counting X-Ray Imaging System Design
    International Journal on Information Technology · Vol. 1 · No. 4 · pp. 268-270 · Jul. 2013
  42. 19
    Reducing cache and TLB power by exploiting memory region and privilege level semantics
    Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-lien Lu, Ravi Iyer, Tong Li, Seung Eun LEE
    Journal of Systems Architecture · Vol. 59 · No. 6 · pp. 279-295 · Jun. 2013
  43. 18
    Accelerating Histograms of Oriented Gradients descriptor extraction for pedestrian recognition
    Seung Eun LEE, Kyungwon Min, TaeWeon Suh
    Computers and Electrical Engineering · Vol. 39 · No. 4 · pp. 1043-1048 · May 2013
  44. 17
    Adaptive Error Correction in Orthogonal Latin Square Codes for Low-Power, Resilient On-Chip Interconnection Network
    Microelectronics Reliability · Vol. 53 · No. 3 · pp. 509-511 · 2013
  45. 16
    Reusing Existing Resources for Testing a Multi-Processor System-on-Chip
    International Journal of Electronics · Vol. 100 · No. 3 · pp. 355-370 · 2013
  46. 15
    Pipelined CPU Design with FPGA in Teaching Computer Architecture
    JongHyuk Lee, Seung Eun LEE, HeonChang Yu, TaeWeon Suh
    IEEE Trans. on Education · Vol. 55 · No. 3 · pp. 341-348 · Aug. 2012
  47. 14
    CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition
    R. Iyer, S. Srinivasan, O. Tickoo, Z. Fang, R. Illikkal, S. Zhang, V. Chadha, P. Stillwell, Seung Eun LEE
    IEEE Micro · Vol. 31 · No. 3 · pp. 20-31 · Jun. 2011
  48. 13
    CoQoS: Coordinating QoS-Aware Shared Resources in NoC-Based SoCs
    Bin Li, Li Zhao, Ravi Iyer, Li-Shiuan Peh, Michael Leddige, Michael Espig, Seung Eun LEE, Donald Newell
    Journal of Parallel and Distributed Computing · Vol. 71 · No. 5 · pp. 700-713 · May 2011
  49. 12
    Low Power and Resilient On-Chip Interconnection with Orthogonal Latin Squares
    Seung Eun LEE, Yoon Seok Yang, Wei Wu, Gwan S. Choi, Ravi Iyer
    IEEE Design & Test of Computers · Vol. 28 · No. 2 · pp. 30-38 · Apr. 2011
  50. 11
    Area and Power-efficient Innovative Congestion-aware Network-on-Chip Architecture
    Chifeng Wang, Wen-Hsiang Hu, Seung Eun LEE, Nader Bagherzadeh
    Journal of Systems Architecture · Vol. 57 · No. 1 · pp. 24-38 · Jan. 2011
  51. 10
    Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact
    Zhen Fang, Erik G. Hallnor, Bin Li, Michael Leddige, Donglai Dai, Seung Eun LEE, Srihari Makineni, Ravi Iyer
    IEEE Computer Architecture Letters · Vol. 9 · No. 2 · Jul. 2010
  52. 9
    Ray Tracing on a Networked Processor Array
    Jungsook Yang, Seung Eun LEE, Chunyi Chen, Nader Bagherzadeh
    International Journal of Electronics · Vol. 97 · No. 10 · pp. 1193-1205 · Oct. 2010
  53. 8
    Parallel Processing for Block Ciphers on a Fault Tolerant Networkd Processor Array
    Yoon Seok Yang, Jun Ho Bahn, Seung Eun LEE, Jungsook Yang, Nader Bagherzadeh
    International Journal of High Performance Systems Architecture · Vol. 2 · No. 3/4 · pp. 156-167 · 2010
  54. 7
    A High-level Power Model for Network-on-Chip (NoC) Router
    Seung Eun LEE, Nader Bagherzadeh
    Computers & Electrical Engineering · Vol. 35 · No. 6 · pp. 837-845 · Elsevier · Nov. 2009
  55. 6
    A Variable Frequency Link for a Power-Aware Network-on-Chip (NoC)
    Seung Eun LEE, Nader Bagherzadeh
    Integration-the VLSI Journal · Vol. 42 · No. 4 · pp. 479-485 · Elsevier · Sep. 2009
  56. 5
    Clock Boosting Router: Increasing the Performace of an Adaptive Router in Network-on-Chip (NoC)
    Seung Eun LEE, Nader Bagherzadeh
    Scientia Iranica · Vol. 15 · No. 6 · pp. 579-588 · Dec. 2008
  57. 4
    On Design and Application Mapping of A Network-on-Chip (NoC) Architecture
    Jun Ho Bahn, Seung Eun LEE, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh
    Parallel Processing Letters (PPL) · Vol. 18 · pp. 239-255 · Jun. 2008
  58. 3
    Design of a router for network-on-chip
    Jun Ho Bahn, Seung Eun LEE, Nader Bagherzadeh
    International Journal of High Performance Systems Architecture · Vol. 1 · No. 2 · pp. 98-105 · 2007
  59. 2
    A 32-bit High Performance VLIW DSP for Software Defined Radio Applications
    Seung Eun LEE, Yong- Mu Jeong
    IEICE Transactions on Electronics · Vol. E87-C · No. 11 · Nov. 2004
  60. 1
    Development of a Novel Current Controlled Organic Light Emitting Diode (OLED)
    Seung Eun LEE, Won-Seok OH, Sung-Chul LEE, Jong-Chan CHOI
    IEICE Transactions on Electronics · Vol. E85-C · No. 11 · pp. 1940-1944 · Nov. 2002