← Alumni
Yeongseob Jeong

Yeongseob Jeong (2014)

Dept. of Electronic and Information Engineering Seoul National University of Science and Technology
232 Gongneung-ro, Nowon-gu, 01811, Seoul, KOREA

Education & Experiences

Researcher, Wipro
2014.02, M.S. in Electronic Engineering, Seoul National University of Science and Technology.
- Thesis Title : "Simulation-based Fault Analysis for Resilient System-on-Chip Design"
2012.06, Teaching Assistant, Training Program for Digital Front-End Design Professional Engineer, ETRI.
2012.03 - 2013.06, Teaching Assistant, Dept. of Electronic and Information Engineering, Seoul National University of Science and Technology.
2012.02, B.S. in Electronic and Information Engineering, Seoul National University of Science and Technology.
2010.10 - 2014.02, Research Assistant, SoC Platforms Lab., Seoul National University of Science and Technology.

Research Interests

1. Fault Tolerant Processor
- Soft Error Rate Modeling on Block and Gate Level
- Low Overhead Error Correction.
- Hardware Redundancy, Duplication.
2. Network on Chip
- XY & YX Mesh Routing.
- Deadlock Free Architecture.
3. ARM Cortex M0 Integration
- Peripheral IP desing (UART, I2C, Memory Controller, etc)
- Implementation on FPGA
- RTOS Porting. UC/OS2

Projects

  1. A rehabilitation support system with a shoe-type device using foot pressure measurement (capstone design)
  2. Network on chip, mesh network design
  3. Development of virtual memory system on multi-server and application software to provide realtime processing of exponential transaction and high availability service

Awards

  • 1. 2011.11 - An award for excellence in capstone design.

Publications

International Journals

  1. 5
    Simulation-Based Fault Analysis for Resilient System-On-Chip Design
    Changyeop Han, Yeongseob Jeong, Seung Eun LEE
    Journal of Information and Communication Convergence Engineering (JICCE) · Vol. 19 · No. 3 · pp. 175-179 · Sep. 2021
  2. 4
    Survey of Fault-Injection Techniques for Resilient System-on-Chip Design
    Yeongseob Jeong, Seongmo Lee, Seung Eun LEE
    International Journal of Applied Engineering Research (IJAER) · Vol. 10 · No. 17 · pp. 38377-38383 · Oct. 2015
  3. 3
    Implementation of Smart U-Health Care System
    Yeongseob Jeong, Yeong Ju Kwon, Seung Eun LEE
    Information Journal · Vol. 17 · No. 10 · pp. 4911-49916 · (A) · Oct. 2014
  4. 2
    Deadlock-free XY-YX router for On-Chip Intertconnection Network
    Yeongseob Jeong, Seung Eun LEE
    IEICE Electronics Express (ELEX) · Vol. 10 · No. 20 · pp. 20130699 · Oct. 2013
  5. 1
    IPFM: Intelligent Pressure Foot-Mouse
    Hyun Min CHOI, Yeongseob Jeong, SeungJun SON, Jae Gi Son, Seung Eun LEE
    International Journal of Multimedia and Ubiquitous Engineering (IJMUE) · Vol. 8 · No. 5 · pp. 31-40 · Sep. 2013

International Conferences

  1. 7
    Design of a Deadlock-free XY-YX Router for Network-on-Chip
    SangMuk Lee, Eun Nu Ri Ko, Yeongseob Jeong, Seung Eun LEE
    13th International Conference on Information Technology (ITNG) · Las Vegas, Nevada · Apr. 2016
  2. 6
    In-time Transaction Accelerator Architecture for RDBMS
    Sujin Kim, Seongmo Lee, Jihoon Jang, Yeongseob Jeong, Sangdon Kim, Seung Eun LEE
    Lecture Notes in Electrical Engineering · Vol. 260 · pp. 329-334 · 2013
  3. 5
    Intra-Body Communication for Personal Area Network
    Sangdon Kim, Ju Seong LEE, Yeongseob Jeong, Jihoon Jang, Seung Eun LEE, SangMuk Lee
    Lecture Notes in Electrical Engineering · Vol. 260 · pp. 335-339 · 2013
  4. 4
    SDRAM Controller for Retention Time Analysis in Low Power Signal Processor
    Sangdon Kim, Yeongseob Jeong, Ju Seong LEE, Seung Eun LEE
    Lecture Notes in Electrical Engineering · Vol. 222 · pp. 303-309 · 2013
  5. 3
    Hardware Overhead vs. Performance of Matrix Multiplication on FPGA
    Ju Seong LEE, Sangdon Kim, Yeongseob Jeong, Seung Eun LEE
    Lecture Notes in Electrical Engineering · Vol. 222 · pp. 295-302 · 2013
  6. 2
    Foot Motion Recognition for Human-Computer Interaction
    Hyun Min CHOI, Yeongseob Jeong, SeungJun SON, Seung Eun LEE
    Lecture Notes in Electrical Engineering · Vol. 221 · pp. 529-533 · 2013
  7. 1
    Ambulatory Patern Extraction for U-Health Care
    Yeongseob Jeong, SeungJun SON, Hyun Min CHOI, Seung Eun LEE
    Communications in Computer and Information Science · Vol. 316 · pp. 626-630 · 2012

Copyrights

Registration

  1. 5
    Method of Analyzing Error Rate in System-on-Chip
    US 9,671,447 B2, Jun. 2017, USA (right owned by SeoulTech)
  2. 4
    SoC에서의 오류율 분석 방법
    Method for analyzing error rate in System on Chip
    Registration No. 10-1544649, Aug. 2015, Korea (right owned by SeoulTech)
  3. 3
    SoC에서의 게이트 레벨 오류 모델링 방법
    Method for modeling error of level of gate in System on Chip
    Registration No. 10-1492743, Feb. 2015, Korea (right owned by SeoulTech)
  4. 2
    네트워크 온 칩 성능 향상을 위한 XY-YX 라우팅 장치 및 방법
    XY-YX routing apparatus and method for enhancing performance of Network-on-Chip
    Registration No. 10-1297533, Aug. 2013, Korea (right owned by SeoulTech)
  5. 1
    SoC 에서의 오류 모델링 방법
    Methdod for fault modeling in SoC
    Registration No. 10-1297484, Aug. 2013, Korea (right owned by SeoulTech)

Application

  1. 1
    Method of Processing Immediate Value in EISC Processor
    Application No. 13,874,232, Apr. 2013, USA (right owned by SeoulTech, Korea Univ., and AD Chips)

Copyrighted Softwares

  1. 5
    시스템 반도체 소프트에러 모델링을 위한 오류율 추출 프로그램
    Registration No. C-2013-015330, July 2013, Korea (right owned by SeoulTech)
  2. 4
    프로세서의 소프트에러 모델링을 위한 오류율 추출 프로그램
    Registration No. C-2013-015329, July 2013, Korea (right owned by SeoulTech)
  3. 3
    시스템반도체의 블록 데이터 추출 프로그램
    Registration No. C-2013-015328, July 2013, Korea (right owned by SeoulTech)
  4. 2
    교착상태가 없는 엑스와이-와이엑스 (XY-YX) 메쉬 라우터 회로
    Registration No. C-2013-000688, Jan. 2013, Korea (right owned by SeoulTech)
  5. 1
    이차원 메쉬 토폴로지를 지원하는 네트워크 온 칩 회로 생성 및 성능 검증 프로그램
    Registration No. C-2013-000687, Jan. 2013, Korea (right owned by SeoulTech)

Presentations

  • 1. "FPGA remote laboratory for hardware e-learning courses". SPL meeting. Jan. 2011.
  • 2. "Shoe-Mouse: An Integrated Intelligent Shoe". SPL meeting. Feb. 2011.
  • 3. "Development of a rehabilitation support system with a shoe-type measurement device for walking".SPL meeting. Jul. 2011.
  • 4. "Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip".SPL meeting. Jan. 2012.
  • 5. "Fault-Tolerant Routing Algorithm for Network-on-Chip Based on Dynamic XY Routing". SPL meeting. Feb. 2012.
  • 6. "The future of microprocessor". SPL meeting. Mar. 2012.
  • 7. "The basic of fault tolerance". SPL meeting. Jul. 2012.
  • 8. "Redundancy_Hardware Fault Tolerance". SPL meeting. Jul. 2012.
  • 9. "Time Redundancy". SPL meeting. Sep. 2012.
  • 10. "Dual-NI Architectures for Fault Tolerant NoC". SPL meeting. Apr. 2013.
  • 11. "Verification and fault synthesis algorithm at switch-level". SPL meeting. Jul. 2013.

Skills

- EDA tools: ModelSim, PSpice, ORCAD, Quartus, Xilinx ISE, NC verilog, VCS
- FPGA Prototyping: Altera, Xilinx
- Analysis Language: MATLAB
- High-level Computer Language: C
- Microprocessor: Atmega128, ARM
- Linux server management

Training

2011.07 - Orcad PCB Education, Nine plus company.
2012.02 - Front-End / Back-End Design Education For the Production of SoC Chip, ETRI.
2012.01 - HW Implementation of SRIR Techniques, ETRI
2012.06 - Concept of semiconductor systems design, ETRI
2012.09 - ARM Core-based design and applications, ETRI

Courses

Circuit Designs, Digital System Design, Logic circuits, engineering programming, electric magnetism, microwave engineering, signal and systems
electronic circuits, microprocessors, RF circuit design, computer applications, system design, digital signal processing, image processing
semiconductor engineering, control engineering, computer architecture