← Alumni
Jihoon Jang

Jihoon Jang (2016)

Dept. of Electronic and Information Engineering Seoul National University of Science and Technology
232 Gongneung-ro, Nowon-gu, 01811, Seoul, KOREA

Education & Experiences

Research Engineer, Hyundai MOBIS.
2016.02, Master of Science in Electronic Engineering, Seoul National University of Science and Technology.
- Thesis Title : "A Study on Hardware Acceleration of Lempel-Ziv Compression Algorithm"
2014.02 - 2014.11, Researcher, Software Device Research Center, Korea Electronics Technology Institute.
2014.02, Bachelor of Science in Electronic Engineering, Seoul National University of Science and Technology.
2012.03 - 2016.02, Research Assistant, SoC Platforms Lab., Seoul National University of Science and Technology.

Research Interests

- Hardware Accelerators
- Network-on-Chips

Projects

  1. 폭증스트림 데이터의 실시간 고가용 처리 서비스를 제공하는 다수 서버 분산 메모리의 통합 캐쉬 가상화 기술 기반 특화 응용 SW 개발
    미래창조과학부, 2012-2015.
  2. 단일 노드 48TB 이상을 지원하는 개방형 하둡 스토리지 어플라이언스 개발
    미래창조과학부, 2013-2015.
  3. 주력산업 고도화를 위한 SoC 결합형 임베디드SW 핵심기술 개발 및 산업생태계 개선
    산업통상자원부, 2014-2015.
  4. 스마트키 기능을 포함하는 밴드형 웨어러블 디바이스 및 핵심기술 개발
    산업통상자원부, 2014-2015.

Awards

  • 2012. Wearable Computer Contest - Silver Award (Hosted by Ministry of Knowledge Economy)
  • 2014. Altera Design Contest - Excellence Award (Hosted by Altera Korea and Axios)

Publications

International Journals

  1. 2
    Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression
    IEICE Electronics Express (ELEX) · Vol. 14 · No. 11 · pp. 20170399 · 2017
  2. 1
    Design of a DMA Controller for Loss-less Image Processing
    IDEC Journal of Integrated Circuits and Systems (JICAS) · Vol. 2 · No. 2 · pp. 1-6 · 2016

International Conferences

  1. 13
    Live Demonstration : An FPGA Based Hardware Compression Accelerator for Hadoop System
    13th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · Jeju · Oct. 2016
  2. 12
    A DMA Controller for Loss-less Image Processing
    13th International SoC Design Conference (ISOCC CDC) · Jeju · Oct. 2016
  3. 11
    A LZ4 Compression Acceleration Engine
    13th International SoC Design Conference (ISOCC CDC) · Jeju · Oct. 2016
  4. 10
    Accelerating JPEG Image Compression for Audio Video Bridging
    13th International SoC Design Conference (ISOCC CDC) · Jeju · Oct. 2016
  5. 9
    An FPGA based Compression Accelerator for Forex Trading System
    13th International Conference on Information Technology (ITNG) · pp. 711-720 · Las Vegas, Nevada · Apr. 2016
  6. 8
    Design of an EMG Recognition System for Human-Smartphone Interface
    12th International SoC Design Conference (ISOCC) · pp. 337-338 · Gyeongju · Nov. 2015
  7. 7
    VGA Controller for Zero Client SoC
    International SoC Design Conference Chip Design Contest (ISOCC CDC) · Gyeongju · Nov. 2015
  8. 6
    LZ4 Compression Engine
    International SoC Design Conference Chip Design Contest (ISOCC CDC) · Gyeongju · Nov. 2015
  9. 5
    Accelerating Forex Trading System Through Transaction Log Compression
    11th International SoC Design Conference (ISOCC) · pp. 74-75 · Jeju · Nov. 2014
  10. 4
    Compression Accelerator for Hadoop Appliance
    Sangdon Kim, Seongmo Lee, SangMuk Lee, Jihoon Jang, Jae Gi Son, Yonug Hwan Kim, Seung Eun LEE
    Lecture Notes in Computer Science · Vol. 8662 · pp. 416-423 · 2014
  11. 3
    In-time Transaction Accelerator Architecture for RDBMS
    Lecture Notes in Electrical Engineering · Vol. 260 · pp. 329-334 · 2013
  12. 2
    Intra-Body Communication for Personal Area Network
    Lecture Notes in Electrical Engineering · Vol. 260 · pp. 335-339 · 2013
  13. 1
    mrGlove: FPGA-based data glove for heterogeneous devices
    Lecture Notes in Electrical Engineering · Vol. 260 · pp. 341-345 · 2013

Korean Conferences

  1. 5
    하둡 시스템을 위한 FPGA기반의 하드웨어 압축 가속기
    2016년 SoC 학술대회 · May 2016
  2. 4
    하둡 클러스터를 위한 마이크로서버 구조 연구
    장지훈, 김영환, 전기만, 손재기, 이승은
    2015년 대한전자공학회 하계종합학술대회 (IEIE) · Jun. 2015
  3. 3
    오디오 비디오 브릿징을 위한 고속 JPEG 코덱 설계
    2015년 SoC 학술대회 · May 2015
  4. 2
    LZ4 Compression Accelerator for Hadoop Systems
    제1회 Korea ACM SIGARCH Chapter 워크샵 · Jan. 2015
  5. 1
    FX 마진거래 시스템을 위한 하드웨어 가속기 구조
    2014년 SoC 학술대회 · May 2014

Copyrights

Registration

  1. 2
    하둡 기반 하드웨어 압축 고속화 장치 및 방법
    Apparatus and Method for Accelerating Hardware Compression Based on Hadoop
    Registration No. 10-1727508, Apr. 2017, Korea (right owned by SeoulTech)
  2. 1
    문자열 압축 및 해제를 위한 방법 및 장치
    METHOD AND APPARATUS FOR ENCODING AND DECODING STRINGS
    Registration No. 10-1705461, Feb. 2017, Korea (right owned by SeoulTech)

Application

  1. 1
    Apparatus and Method for Accelerating Hardware Compression Based on Hadoop
    Application No. 6-1-2015-0043962-65, Aug. 2015, PCT (right owned by SeoulTech and dfocus)

Copyrighted Softwares

  1. 1
    고속 엘지4(LZ4) 압축회로 프로그램
    Registration No. C-2015-018807, Aug. 2015, Korea (right owned by SeoulTech)

Chips

2015

LZ4 Compression Engine
Jihoon Jang, Seongmo Lee, SangMuk Lee, Jungwoo Shin, Seung Eun LEE
Tech
Magnachip hynix 0.18um CMOS (1-poly 6-metal)
Tape-out
2015.09.07
Freq
50MHz
Core
3.8mm x 3.8mm
Power
1.8V, 3.3V
DMA Controller for Image Data Processing
Seongmo Lee, Jihoon Jang, Seung Eun LEE
Tech
Magnachip hynix 0.35um CMOS (2-poly 4-metal)
Tape-out
2015.06.08
Freq
50MHz
Core
3mm x 2mm
Power
3.3V

2014

LZ4 Compression Accelerator for Hadoop Storage Appliance
Jihoon Jang, Seung Eun LEE
Tech
Magnachip hynix 0.18um CMOS (1-poly 6-metal)
Tape-out
2014.11.24
Freq
50MHz
Core
0.6mm x 1.5mm
Power
1.8V
Cloud Device SoC for Zero-Client
Sangdon Kim, Jihoon Jang, Seung Eun LEE
Tech
Magnachip hynix 0.35um CMOS (2-poly 4-metal)
Tape-out
2014.06.30
Freq
50MHz
Core
1.8mm x 1.6mm
Power
3.3V

Presentations

  • 7. "Dynamic Traffic Distribution among Hierarchy Levels in Hierarchical Networks-on-Chip", SPL meeting. Oct. 2014.
  • 6. "ASIC Back-end design(Astro)", SPL meeting. Mar. 2014.
  • 5. "Analysis and evaluation of circuit switched NoC and packet switched NoC", SPL meeting. Jan. 2014.
  • 4. "Client Rendering Method for Desktop Virtualization Services", SPL meeting. Apr. 2013.
  • 3. "Flattened Butterfly Topology for On-Chip Networks", SPL meeting. Mar. 2013.
  • 2. "NoC-Out: Microarchitecting a Scale-Out Processor", SPL meeting. Jan. 2013.
  • 1. "Cloud Computing", SPL meeting. Jul. 2012.

Skills

- FPGA Prototyping
- ASIC Design
- EDA tools: OrCAD PSpice, Design Compiler, VCS, Astro
- Analysis Language: MATLAB, LabVIEW
- High-level Computer Language: C, JAVA

Training

2013.01.23 - 01.24 IAR Embedded Workbench Basic training, IAR Systems.
2013.01.29 - 01.31 PrimeTime Basic training, ETRI IT-SoC Academy.
2013.05.08 - 05.10 ZYNQ Basic training, RAPA ATIC.
2014.02.11 - 02.13 IC Compiler Basic training, IDEC.
2014.07.21 - 07.25 MPW Design training, IDEC.
2014.11.15 CMOS 아날로그 집적회로 실무를 위한 이론 및 실습 I, IDEC.
2014.11.22 CMOS 아날로그 집적회로 실무를 위한 이론 및 실습 II, IDEC.
2015.01.12 - 01.14 Full-Custom 설계 Flow 교육, IDEC.
2016.01.04 - 02.04 인피니언 연계 자동차용 반도체 전문인력 양성 과정, Infineon Korea.

Courses

Circuit Analysis, Electro Magnetics, Logic Design, Computer Application System Design, Microwave Engineering, Microprocessor,
Signal Processing, Digital Signal Processing, Electronic Circuit, Control Engineering, Computer Architecture, Power Electronics,
Biomedical Instrumentation, Operationg systems, Internet Protocol, Communication System, Image Processing, Embedded Systems,
Capstone Design, Thin-film Transistor Engineering, Probability and Random Process, Advanced Computer Architecture, Real-time Operating Systems,
Topics in Artificial Intelligence, Network-on-Chip Design, Digital Signal Processor Application, and Fault Tolerant Processor Design