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Dayoung Lee

Dayoung Lee

Dept. of Electronic and Information Engineering Seoul National University of Science and Technology
232 Gongneung-ro, Nowon-gu, 01811, Seoul, KOREA

Education & Experiences

2026.03 - present, Graduate Student, Dept. of Electronic Engineering, Seoul National University of Science and Technology.
2024.05 - present, Research Assistant, Computer Architecture Lab, Seoul National University of Science and Technology.
2026.02 - B.S. in Electronic Engineering, Seoul National University of Science and Technology.
2022.03 - 2026.02, Undergraduate Student, Dept. of Electronic, Seoul National University of Science and Technology.

Research Interests

Processor Architecture
Efficient AI
Ternary LLM

Projects

  1. Development of real time monitering sensor for gas pipe
    Ministry of Trade, Industry and Energy, Korea, 2022-2026.
  2. Development for Processing Software on AI Semiconductor Devices
    Ministry of Science and ICT, Korea, 2022-2029.

Publications

International Journals

  1. 1

International Conferences

  1. 4
    A Pipelined Multi-Bank GEMM Accelerator for Memory Bottleneck Mitigation
    Dayoung Lee, Chaebin Lee, Jaeseong Kim, Seung Eun LEE
    International Conference on Parallel Architectures and Compilation Techniques (PACT src) · Irvine, CA · Sep. 2025
  2. 3
  3. 2
    FPGA Based Approximate Vector Operation Accelerator for VLMs
    Raehyeong Kim, Chaebin Lee, Dayoung Lee, Yueri Jeong, Seung Eun LEE
    International Conference on Electronics, Information, and Communication (ICEIC) · Osaka · Jan. 2025
  4. 1
    Flexible NTT/iNTT Accelerator Based on Montgomery Reduction
    Jinyeol Kim, Jinyoung Shin, Seongmo An, Chaebin Lee, Dayoung Lee, Seung Eun LEE
    International Conference on Consumer Electornics (ICCE) · Las Vegas, NV · Jan. 2025

Korean Conferences

  1. 3
    Analysis of Training Dataset Construction Methods for Improving the Performance of the Edge AI Processor
    이채빈, 김재성, 이다영, 안성모, 박정민, 이승은
    Korean Association Data Science, Spring Joint Academic Conference (KADS) · Yeosu · Jun. 2025
  2. 2
    FP8-FP16 혼합 정밀도 기반의 MobileNetV1 추론 성능 분석
    김재성, 이채빈, 이다영, 이승은
    The Institute of Electronics and Information Engineers · May 2025
  3. 1

Copyrights

Copyrighted Softwares

  1. 5
    인공지능 프로세서(Processor)의 효과적인 활용을 위한 그래픽 사용자 인터페이스(Graphic User Interface) 기반 시뮬레이터(Simulator)
    Registration No. C-2025-046318, Nov. 2025, Korea (right owned by SeoulTech)
  2. 4
    비전 트랜스포머(Vision Transformer) 전용 멀티-헤드 어텐션(Multi-Head Attention) 가속기
    Registration No. C-2025-045292, Oct. 2025, Korea (right owned by SeoulTech)
  3. 3
    인텔리노(Intellino): 경량 엣지(Edge) 인공지능 프로세서(Processor)
    Registration No. C-2025-045291, Oct. 2025, Korea (right owned by SeoulTech)
  4. 2
    k-최근접이웃 알고리즘(Algorithm) 기반 인공지능 프로세서(Processor)를 활용한 정맥 인식 도어락(Door Lock)
    Registration No. C-2025-045290, Oct. 2025, Korea (right owned by SeoulTech)
  5. 1
    인공지능 가속기용 파이프라인(Pipeline) 시뮬레이터(Simulator)
    Registration No. C-2025-045303, Oct. 2025, Korea (right owned by SeoulTech)

Chips

2026

A Networked Processor Array Supporting High-Bandwidth Host Interface
Jinyeol Kim, Raehyeong Kim, Jongwon Oh, Dayoung Lee, Seongmo An, Seung Eun LEE
Tech
Samsung 28nm FD-SOI
Tape-out
2026.03.23
Freq
100MHz
Core
4mm x 4mm
Power
1.1V/1.8V

2025

A Reconfigurable AI Processor Executing Lightweight Algorithms for Sequential Data Applications
Raehyeong Kim, Jinyoung Shin, Jinyeol Kim, Dayoung Lee, Joungmin Park, Seung Eun LEE
Tech
Samsung 28nm FD-SOI
Tape-out
2025.09.25
Freq
100MHz
Core
4mm x 4mm
Power
1.1V/1.8V

Student Research Competition

Presentations

Awards

Skills

- High-level Programming Language: Python, C/C++
- Hardware Description Language: Verilog HDL
- FPGA Design Tools: Quartus II, Vivado
- EDA Tools:
Front-end: Design Compiler, VCS, QuestaSim, PrimeTime, Formality
Back-end: ICC2, Calibre, StarRC, ECO
- Circuit Entry Tool: Virtuoso Schematic Editor
- Layout Tool: Virtuoso Layout Suite

Training

2026.07.06-07.07 [IDEC] 고성능 컴퓨터 시스템 구조
2025.11.19 삼성 HBM-PIM 이론 및 실습
2025.07.07-07.08 [IDEC] Verilog HDL을 사용한 CNN의 FPGA 구현
2025.06.16-06.17 [IDEC] Catapult High Level Synthesis
2025.01.14-01.16 [IDEC] System Verilog

Graduate Courses

CMOS Power Management IC Design, Advanced Artificial Intelligence Processor
Special Lecture on Artificial Intelligence, Advanced Computer Architecture, Resilient Processor Design

Undergraduate Courses

Capstone Design, Operating System
Digital System Design, Computer Architecture, Machine Learining, Deep Learning, Data Structure and Algorithm
Computer Programming (C Programming), Engineering Mathmatics, Electrical and Electronic Experiment
Electromagnetics, Digital Logic Circuit, Signal and Systems, Circuit Theory
Electronic Circuits, Digital System Design, Machine Learning, Digital Signal Processing