← Alumni
Sangho Lee

Sangho Lee (2025)

Dept. of Electronic Engineering Seoul National University of Science and Technology
232 Gongneung-ro, Nowon-gu, 01811, Seoul, KOREA

Education & Experiences

2025.09 - present, Engineering, Wipro
2026.02, M.S. in Electronic and Engineering, The Graduate School, Seoul National University of Science and Technology.
2024.02, B.S. in Electronic and Information Engineering, Seoul National University of Science and Technology.
2022.07 - 2026.02, Research Assistant, SoC Platform Lab, Seoul National University of Science and Technology.

Projects

  1. Development of real time monitoring sensor for gas pipe
    Ministry of Trade, Industry and Energy, Korea, 2022-2026.
  2. Development of DRAM PIM semiconductor technology for enhanced computing function for edge
    Ministry of Science and ICT, Korea, 2022-2025.
  3. Next-Generation System Semiconductor Design Engineer Development Program
    Ministry of Trade, Industry and Energy, Korea, 2021-2026.
  4. Development for Processing Software on AI Semiconductor Devices
    Ministry of Science and ICT, Korea, 2022-2029.
  5. Developed proximity/healthcare convergence sensor SoC for TWS (True Wireless Stereo)
    Ministry of Trade, Industry and Energy, Korea, 2021-2023.

Publications

International Journals

  1. 4
  2. 3
  3. 2
  4. 1

International Conferences

  1. 5
    Analysis of the Impact of LFSR Architecture on Accuracy of Stochastic Computing Processors
    International Symposium on Quality Electronic Design (ISQED) · California · Apr. 2025
  2. 4
    Point Cloud Clustering System with DBSCAN Algorithm for Low-Resolution LiDAR
    International Conference on Consumer Electronics (ICCE) · Las Vegas · Jan. 2024
  3. 3
    PIMCoSim: HW/SW Co-Simulator for Exploring Processing In Memory Architectures
    ACM Student Research Competition (ACM SRC @PACT) · Vienna · Oct. 2023
  4. 2
    An Approach for Lightweight and Error-Tolerant Binocular Stereo Matching with Stochastic Computing
    ACM Student Research Competition (ACM SRC @MICRO) · Toronto · Oct. 2023
  5. 1
    AI Processor based Data Correction for Enhancing Accuracy of Ultrasonic Sensor
    International Conference on Artificial Intelligence Circuits and Systems (AICAS) · Hangzhou · Jun. 2023

Korean Conferences

  1. 1

Copyrights

Copyrighted Softwares

  1. 2
    고정식 라이다(LiDAR)의 특성을 이용한 격자 밀도 기반 3차원 점군 클러스터링(Clustering) 가속기
    Registration No. C-2024-047141, Nov. 2024, Korea (right owned by SeoulTech)
  2. 1
    인공지능 가속기를 활용한 초음파 센서 데이터 정확도 향상 분석 프로그램
    Registration No. C-2023-023355, May. 2023, Korea (right owned by SeoulTech)

Chips

2025

A Pipelined WebAssembly Processor Architecture for Accelerated Execution in Embedded IoT Systems
Jinyeol Kim, Jongwon Oh, Raehyeong Kim, Chaebin Lee, Sangho Lee, Seung Eun LEE
Tech
Samsung 28nm FD-SOI
Tape-out
2025.09.25
Freq
100MHz
Core
4mm x 4mm
Power
1.1V/1.8V
A Low-Power Point Cloud Clustering System with a DBSCAN Clustering Accelerator based on Cortex-M0
Sangho Lee, Seongmo An, Raehyeong Kim, Jongwon Oh, Seung Eun LEE
Tech
Samsung 28nm FD-SOI
Tape-out
2025.02.02
Freq
100MHz
Core
4mm x 4mm
Power
1.1V/1.8V

2024

An Error Correcting Code Encoder Utilizing Orthogonal Latin Square Code for HBM Application
Yueri Jeong, Sangho Lee, Seongmo An, Jinyeol Kim, Seung Eun LEE
Tech
Samsung 28nm FD-SOI
Tape-out
2024.09.09
Freq
50M/200MHz
Core
4mm x 4mm
Power
1.1V/1.8V
Convolution-based Feature Extractor Equipped with an Improved Systolic Array Architecture
Joungmin Park, Sangho Lee, Jinyoung Shin, Raehyeong Kim, Seung Eun LEE
Tech
Samsung 28nm LPP
Tape-out
2024.07.18
Freq
50M/200MHz
Core
4mm x 4mm
Power
1.2V

Student Research Competition

Presentations

  • 1. "Point Cloud Clustering System with DBSCAN Algorithm for Low-Resolution LiDAR",
    Sangho Lee, Seongmo An, Raehyeong Kim, Jongwon Oh and Seung Eun Lee,
    2024 International Conference on Consumer Electronics (ICCE), Jan. 2024.

Awards

Skills

- High-level Programming Language: C, Python, Matlab
- Hardware Description Language: Verilog
- Functional Verification Tools: VCS, ModelSim, Verdi
- Circuit Entry Tool: Virtuoso Schematic Editor
- RTL Synthesis Tools: Design Compiler, Quartus II
- Equivanlence Checking Tool: Formality
- Place & Route Tool: IC Compiler II
- Physical Verification Tool: Calibre DRC
- Layout Verification Tool: Calibre LVS
- Static Timing Analysis Tool: PrimeTime
- Layout Parasitic Extraction Tools: StarRC, Calibre PEX
- Layout Tool: Virtuoso Layout Suite
- PCB Design Tools: OrCAD Pspice Designer, Allegro PCB Designer

Training

2025.01.08-01.10 [IDEC] Cell-Based Chip Design Front-End
2024.11.20-11.22 [KAIST AI-PIM] Samsung HBM PIM Principles and Practice
2024.11.11-11.13 [KAIST AI-PIM] SK Hynix AiM(Accelerator in Memory) Principles and Practice
2024.05.30-05.31 [IDEC] Design and Verification of AMBA AXI and AXI-Stream
2024.05.22-05.24 [IDEC] Understanding and Designing AMD Xilinx FPGA Hardware Configuration
2023.04.24-04.25 [IDEC, Siemens EDA] Catapult High Level Synthesis Training to Implement/Create Verilog RTL from C/C++ algorithm design
2023.02.20-02.22 [IDEC] Algebraic Error-Correcting Codes
2023.02.06-02.10 [KIRD] Basic Semiconductor Design Curriculum - PCB Artwork with OrCAD PCB Editor(Allegro)
2022.11.28-11.29 [IDEC] Deep-Learning Processing Unit Design and Implementation
2022.08.16-08.25 [Infineon] Professional Training Course for Automotive Semiconductor, Korea Semiconductor Industry Association
2022.08.08-08.10 [Infineon] Basic Training Course for Automotive Semiconductor, Korea Semiconductor Industry Association

Courses

Digital System Design, Control Systems Engineering, Logic Circuit,
Electronic Circuits, Electromagnetics, Semiconductor Engineering, Digital Signal Processing,
Computer Programming(C Programming), Engineering Mathmatics,
Circuit Theory, Signal System, Electrical and Electronic Experiment,
Computer Architecture, Android Programing(Java Programming),
Semiconductor Devices Application and Design,
Operating System, Machine Learning